From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Li8GD-0006S8-7A for qemu-devel@nongnu.org; Fri, 13 Mar 2009 10:21:17 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Li8G5-0006KW-7a for qemu-devel@nongnu.org; Fri, 13 Mar 2009 10:21:13 -0400 Received: from [199.232.76.173] (port=50619 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Li8G4-0006K0-PH for qemu-devel@nongnu.org; Fri, 13 Mar 2009 10:21:08 -0400 Received: from mel.act-europe.fr ([212.99.106.210]:53561) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Li8G4-0002UF-0J for qemu-devel@nongnu.org; Fri, 13 Mar 2009 10:21:08 -0400 From: Tristan Gingold Date: Fri, 13 Mar 2009 15:20:27 +0100 Message-Id: <1236954043-91856-9-git-send-email-gingold@adacore.com> In-Reply-To: <1236954043-91856-8-git-send-email-gingold@adacore.com> References: <1236954043-91856-1-git-send-email-gingold@adacore.com> <1236954043-91856-2-git-send-email-gingold@adacore.com> <1236954043-91856-3-git-send-email-gingold@adacore.com> <1236954043-91856-4-git-send-email-gingold@adacore.com> <1236954043-91856-5-git-send-email-gingold@adacore.com> <1236954043-91856-6-git-send-email-gingold@adacore.com> <1236954043-91856-7-git-send-email-gingold@adacore.com> <1236954043-91856-8-git-send-email-gingold@adacore.com> Subject: [Qemu-devel] [PATCH 08/24] Allow 5 mmu indexes. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tristan Gingold This is necessary for alpha because it has 4 protection levels and pal mode. Signed-off-by: Tristan Gingold --- exec.c | 30 +++++++++++++++++++++++++----- softmmu_exec.h | 29 ++++++++++++++++++++++++----- 2 files changed, 49 insertions(+), 10 deletions(-) diff --git a/exec.c b/exec.c index 05244a9..10f04e2 100644 --- a/exec.c +++ b/exec.c @@ -1759,12 +1759,18 @@ void tlb_flush(CPUState *env, int flush_global) env->tlb_table[2][i].addr_read = -1; env->tlb_table[2][i].addr_write = -1; env->tlb_table[2][i].addr_code = -1; -#if (NB_MMU_MODES == 4) +#endif +#if (NB_MMU_MODES >= 4) env->tlb_table[3][i].addr_read = -1; env->tlb_table[3][i].addr_write = -1; env->tlb_table[3][i].addr_code = -1; #endif +#if (NB_MMU_MODES >= 5) + env->tlb_table[4][i].addr_read = -1; + env->tlb_table[4][i].addr_write = -1; + env->tlb_table[4][i].addr_code = -1; #endif + } memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); @@ -1808,9 +1814,12 @@ void tlb_flush_page(CPUState *env, target_ulong addr) tlb_flush_entry(&env->tlb_table[1][i], addr); #if (NB_MMU_MODES >= 3) tlb_flush_entry(&env->tlb_table[2][i], addr); -#if (NB_MMU_MODES == 4) +#endif +#if (NB_MMU_MODES >= 4) tlb_flush_entry(&env->tlb_table[3][i], addr); #endif +#if (NB_MMU_MODES >= 5) + tlb_flush_entry(&env->tlb_table[4][i], addr); #endif tlb_flush_jmp_cache(env, addr); @@ -1894,10 +1903,14 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, #if (NB_MMU_MODES >= 3) for(i = 0; i < CPU_TLB_SIZE; i++) tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length); -#if (NB_MMU_MODES == 4) +#endif +#if (NB_MMU_MODES >= 4) for(i = 0; i < CPU_TLB_SIZE; i++) tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length); #endif +#if (NB_MMU_MODES >= 5) + for(i = 0; i < CPU_TLB_SIZE; i++) + tlb_reset_dirty_range(&env->tlb_table[4][i], start1, length); #endif } } @@ -1943,10 +1956,14 @@ void cpu_tlb_update_dirty(CPUState *env) #if (NB_MMU_MODES >= 3) for(i = 0; i < CPU_TLB_SIZE; i++) tlb_update_dirty(&env->tlb_table[2][i]); -#if (NB_MMU_MODES == 4) +#endif +#if (NB_MMU_MODES >= 4) for(i = 0; i < CPU_TLB_SIZE; i++) tlb_update_dirty(&env->tlb_table[3][i]); #endif +#if (NB_MMU_MODES >= 5) + for(i = 0; i < CPU_TLB_SIZE; i++) + tlb_update_dirty(&env->tlb_table[4][i]); #endif } @@ -1968,9 +1985,12 @@ static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) tlb_set_dirty1(&env->tlb_table[1][i], vaddr); #if (NB_MMU_MODES >= 3) tlb_set_dirty1(&env->tlb_table[2][i], vaddr); -#if (NB_MMU_MODES == 4) +#endif +#if (NB_MMU_MODES >= 4) tlb_set_dirty1(&env->tlb_table[3][i], vaddr); #endif +#if (NB_MMU_MODES >= 5) + tlb_set_dirty1(&env->tlb_table[4][i], vaddr); #endif } diff --git a/softmmu_exec.h b/softmmu_exec.h index 9cc4535..8eaa0ad 100644 --- a/softmmu_exec.h +++ b/softmmu_exec.h @@ -60,6 +60,7 @@ #include "softmmu_header.h" #undef ACCESS_TYPE #undef MEMSUFFIX +#endif /* (NB_MMU_MODES >= 3) */ #if (NB_MMU_MODES >= 4) @@ -78,12 +79,30 @@ #include "softmmu_header.h" #undef ACCESS_TYPE #undef MEMSUFFIX +#endif /* (NB_MMU_MODES >= 4) */ -#if (NB_MMU_MODES > 4) -#error "NB_MMU_MODES > 4 is not supported for now" -#endif /* (NB_MMU_MODES > 4) */ -#endif /* (NB_MMU_MODES == 4) */ -#endif /* (NB_MMU_MODES >= 3) */ +#if (NB_MMU_MODES >= 5) + +#define ACCESS_TYPE 4 +#define MEMSUFFIX MMU_MODE4_SUFFIX +#define DATA_SIZE 1 +#include "softmmu_header.h" + +#define DATA_SIZE 2 +#include "softmmu_header.h" + +#define DATA_SIZE 4 +#include "softmmu_header.h" + +#define DATA_SIZE 8 +#include "softmmu_header.h" +#undef ACCESS_TYPE +#undef MEMSUFFIX +#endif /* (NB_MMU_MODES >= 4) */ + +#if (NB_MMU_MODES > 5) +#error "NB_MMU_MODES > 5 is not supported for now" +#endif /* (NB_MMU_MODES > 5) */ /* these access are slower, they must be as rare as possible */ #define ACCESS_TYPE (NB_MMU_MODES) -- 1.6.2