[Qemu-devel] [PATCH 15/24] Document which IPR are used by 21264.

[Tristan Gingold <gingold@adacore.com>]

Add defines for IPR bits.

Signed-off-by: Tristan Gingold <gingold@adacore.com>
---
 target-alpha/cpu.h |   96 +++++++++++++++++++++++++++++++++++-----------------
 1 files changed, 65 insertions(+), 31 deletions(-)

diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 5add698..1424185 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -144,51 +144,85 @@ enum {
 /* XXX: TOFIX: most of those registers are implementation dependant */
 enum {
     /* Ebox IPRs */
-    IPR_CC           = 0xC0,
-    IPR_CC_CTL       = 0xC1,
-    IPR_VA           = 0xC2,
-    IPR_VA_CTL       = 0xC4,
-    IPR_VA_FORM      = 0xC3,
+    IPR_CC           = 0xC0,		/* 21264 */
+    IPR_CC_CTL       = 0xC1,		/* 21264 */
+#define IPR_CC_CTL_ENA_SHIFT 32
+#define IPR_CC_CTL_COUNTER_MASK 0xfffffff0UL
+    IPR_VA           = 0xC2,		/* 21264 */
+    IPR_VA_CTL       = 0xC4,		/* 21264 */
+#define IPR_VA_CTL_VA_48_SHIFT 1
+#define IPR_VA_CTL_VPTB_SHIFT 30
+    IPR_VA_FORM      = 0xC3,		/* 21264 */
     /* Ibox IPRs */
-    IPR_ITB_TAG      = 0x00,
-    IPR_ITB_PTE      = 0x01,
-    IPT_ITB_IAP      = 0x02,
-    IPT_ITB_IA       = 0x03,
-    IPT_ITB_IS       = 0x04,
+    IPR_ITB_TAG      = 0x00,		/* 21264 */
+    IPR_ITB_PTE      = 0x01,		/* 21264 */
+    IPR_ITB_IAP      = 0x02,
+    IPR_ITB_IA       = 0x03,		/* 21264 */
+    IPR_ITB_IS       = 0x04,
     IPR_PMPC         = 0x05,
-    IPR_EXC_ADDR     = 0x06,
-    IPR_IVA_FORM     = 0x07,
-    IPR_CM           = 0x09,
-    IPR_IER          = 0x0A,
-    IPR_SIRR         = 0x0C,
-    IPR_ISUM         = 0x0D,
-    IPR_HW_INT_CLR   = 0x0E,
+    IPR_EXC_ADDR     = 0x06,		/* 21264 */
+    IPR_IVA_FORM     = 0x07,		/* 21264 */
+    IPR_CM           = 0x09,		/* 21264 */
+#define IPR_CM_SHIFT 3
+#define IPR_CM_MASK (3ULL << IPR_CM_SHIFT)	/* 21264 */
+    IPR_IER          = 0x0A,		/* 21264 */
+#define IPR_IER_MASK 0x0000007fffffe000ULL
+    IPR_IER_CM       = 0x0B,		/* 21264: = CM | IER */
+    IPR_SIRR         = 0x0C,		/* 21264 */
+#define IPR_SIRR_SHIFT 14
+#define IPR_SIRR_MASK 0x7fff
+    IPR_ISUM         = 0x0D,		/* 21264 */
+    IPR_HW_INT_CLR   = 0x0E,		/* 21264 */
     IPR_EXC_SUM      = 0x0F,
     IPR_PAL_BASE     = 0x10,
     IPR_I_CTL        = 0x11,
-    IPR_I_STAT       = 0x16,
-    IPR_IC_FLUSH     = 0x13,
-    IPR_IC_FLUSH_ASM = 0x12,
+#define IPR_I_CTL_CHIP_ID_SHIFT 24	/* 21264 */
+#define IPR_I_CTL_BIST_FAIL (1 << 23)	/* 21264 */
+#define IPR_I_CTL_IC_EN_SHIFT 2		/* 21264 */
+#define IPR_I_CTL_SDE1_SHIFT 7		/* 21264 */
+#define IPR_I_CTL_HWE_SHIFT 12		/* 21264 */
+#define IPR_I_CTL_VA_48_SHIFT 15	/* 21264 */
+#define IPR_I_CTL_SPE_SHIFT 3		/* 21264 */
+#define IPR_I_CTL_CALL_PAL_R23_SHIFT 20	/* 21264 */
+    IPR_I_STAT       = 0x16,		/* 21264 */
+    IPR_IC_FLUSH     = 0x13,		/* 21264 */
+    IPR_IC_FLUSH_ASM = 0x12,		/* 21264 */
     IPR_CLR_MAP      = 0x15,
     IPR_SLEEP        = 0x17,
     IPR_PCTX         = 0x40,
-    IPR_PCTR_CTL     = 0x14,
+    IPR_PCTX_ASN       = 0x01,	/* field */
+#define IPR_PCTX_ASN_SHIFT 39
+    IPR_PCTX_ASTER     = 0x02,	/* field */
+#define IPR_PCTX_ASTER_SHIFT 5
+    IPR_PCTX_ASTRR     = 0x04,	/* field */
+#define IPR_PCTX_ASTRR_SHIFT 9
+    IPR_PCTX_PPCE      = 0x08,	/* field */
+#define IPR_PCTX_PPCE_SHIFT 1
+    IPR_PCTX_FPE       = 0x10,	/* field */
+#define IPR_PCTX_FPE_SHIFT 2
+    IPR_PCTX_ALL       = 0x5f,	/* all fields */
+    IPR_PCTR_CTL     = 0x14,		/* 21264 */
     /* Mbox IPRs */
-    IPR_DTB_TAG0     = 0x20,
-    IPR_DTB_TAG1     = 0xA0,
-    IPR_DTB_PTE0     = 0x21,
-    IPR_DTB_PTE1     = 0xA1,
+    IPR_DTB_TAG0     = 0x20,		/* 21264 */
+    IPR_DTB_TAG1     = 0xA0,		/* 21264 */
+    IPR_DTB_PTE0     = 0x21,		/* 21264 */
+    IPR_DTB_PTE1     = 0xA1,		/* 21264 */
     IPR_DTB_ALTMODE  = 0xA6,
+    IPR_DTB_ALTMODE0 = 0x26,		/* 21264 */
+#define IPR_DTB_ALTMODE_MASK 3
     IPR_DTB_IAP      = 0xA2,
-    IPR_DTB_IA       = 0xA3,
+    IPR_DTB_IA       = 0xA3,		/* 21264 */
     IPR_DTB_IS0      = 0x24,
     IPR_DTB_IS1      = 0xA4,
-    IPR_DTB_ASN0     = 0x25,
-    IPR_DTB_ASN1     = 0xA5,
-    IPR_MM_STAT      = 0x27,
-    IPR_M_CTL        = 0x28,
+    IPR_DTB_ASN0     = 0x25,		/* 21264 */
+    IPR_DTB_ASN1     = 0xA5,		/* 21264 */
+#define IPR_DTB_ASN_SHIFT 56
+    IPR_MM_STAT      = 0x27,		/* 21264 */
+    IPR_M_CTL        = 0x28,		/* 21264 */
+#define IPR_M_CTL_SPE_SHIFT 1
+#define IPR_M_CTL_SPE_MASK 7
     IPR_DC_CTL       = 0x29,
-    IPR_DC_STAT      = 0x2A,
+    IPR_DC_STAT      = 0x2A,		/* 21264 */
     /* Cbox IPRs */
     IPR_C_DATA       = 0x2B,
     IPR_C_SHIFT      = 0x2C,
-- 
1.6.2