From: Tristan Gingold <gingold@adacore.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 20/25] alpha ld helpers now directly return the value.
Date: Tue, 24 Mar 2009 16:48:02 +0100 [thread overview]
Message-ID: <1237909687-31711-21-git-send-email-gingold@adacore.com> (raw)
In-Reply-To: <1237909687-31711-20-git-send-email-gingold@adacore.com>
Remove _kernel helpers as they can be directly generated.
Replace ld/st_raw with _phys (bug fix).
Change argument name for st helpers (t0/t1 -> val/addr).
Signed-off-by: Tristan Gingold <gingold@adacore.com>
---
target-alpha/helper.h | 22 +++++++---------
target-alpha/op_helper.c | 62 ++++++++++++++++++++-------------------------
target-alpha/translate.c | 32 ++++++++++++------------
3 files changed, 54 insertions(+), 62 deletions(-)
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 4c4855d..7c7278f 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -116,18 +116,16 @@ DEF_HELPER_0(restore_mode, void)
DEF_HELPER_1(ld_virt_to_phys, i64, i64)
DEF_HELPER_1(st_virt_to_phys, i64, i64)
-DEF_HELPER_2(ldl_raw, void, i64, i64)
-DEF_HELPER_2(ldq_raw, void, i64, i64)
-DEF_HELPER_2(ldl_l_raw, void, i64, i64)
-DEF_HELPER_2(ldq_l_raw, void, i64, i64)
-DEF_HELPER_2(ldl_kernel, void, i64, i64)
-DEF_HELPER_2(ldq_kernel, void, i64, i64)
-DEF_HELPER_2(ldl_data, void, i64, i64)
-DEF_HELPER_2(ldq_data, void, i64, i64)
-DEF_HELPER_2(stl_raw, void, i64, i64)
-DEF_HELPER_2(stq_raw, void, i64, i64)
-DEF_HELPER_2(stl_c_raw, i64, i64, i64)
-DEF_HELPER_2(stq_c_raw, i64, i64, i64)
+DEF_HELPER_1(ldl_phys, i64, i64)
+DEF_HELPER_1(ldq_phys, i64, i64)
+DEF_HELPER_1(ldl_l_phys, i64, i64)
+DEF_HELPER_1(ldq_l_phys, i64, i64)
+DEF_HELPER_1(ldl_data, i64, i64)
+DEF_HELPER_1(ldq_data, i64, i64)
+DEF_HELPER_2(stl_phys, void, i64, i64)
+DEF_HELPER_2(stq_phys, void, i64, i64)
+DEF_HELPER_2(stl_c_phys, i64, i64, i64)
+DEF_HELPER_2(stq_c_phys, i64, i64, i64)
#endif
#include "def-helper.h"
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index 4b6ada7..9e9289f 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -1091,64 +1091,58 @@ uint64_t helper_st_virt_to_phys (uint64_t virtaddr)
return physaddr;
}
-void helper_ldl_raw(uint64_t t0, uint64_t t1)
+uint64_t helper_ldl_phys(uint64_t addr)
{
- ldl_raw(t1, t0);
+ return ldl_phys(addr);
}
-void helper_ldq_raw(uint64_t t0, uint64_t t1)
+uint64_t helper_ldq_phys(uint64_t addr)
{
- ldq_raw(t1, t0);
+ return ldq_phys(addr);
}
-void helper_ldl_l_raw(uint64_t t0, uint64_t t1)
+uint64_t helper_ldl_l_phys(uint64_t addr)
{
- env->lock = t1;
- ldl_raw(t1, t0);
+ env->lock = addr;
+ return ldl_phys(addr);
}
-void helper_ldq_l_raw(uint64_t t0, uint64_t t1)
+uint64_t helper_ldq_l_phys(uint64_t addr)
{
- env->lock = t1;
- ldl_raw(t1, t0);
+ env->lock = addr;
+ return ldl_raw(addr);
}
-void helper_ldl_kernel(uint64_t t0, uint64_t t1)
+uint64_t helper_ldl_data(uint64_t addr)
{
- ldl_kernel(t1, t0);
+ /* FIXME: ldl_data won't work in case of fault */
+ cpu_abort(env, "ldl_data not implemented\n");
+ return ldl_data(addr);
}
-void helper_ldq_kernel(uint64_t t0, uint64_t t1)
+uint64_t helper_ldq_data(uint64_t addr)
{
- ldq_kernel(t1, t0);
+ /* FIXME: ldq_data won't work in case of fault */
+ cpu_abort(env, "ldq_data not implemented\n");
+ return ldq_data(addr);
}
-void helper_ldl_data(uint64_t t0, uint64_t t1)
+void helper_stl_phys(uint64_t val, uint64_t addr)
{
- ldl_data(t1, t0);
+ stl_phys(addr, val);
}
-void helper_ldq_data(uint64_t t0, uint64_t t1)
+void helper_stq_phys(uint64_t val, uint64_t addr)
{
- ldq_data(t1, t0);
+ stq_phys(addr, val);
}
-void helper_stl_raw(uint64_t t0, uint64_t t1)
-{
- stl_raw(t1, t0);
-}
-
-void helper_stq_raw(uint64_t t0, uint64_t t1)
-{
- stq_raw(t1, t0);
-}
-
-uint64_t helper_stl_c_raw(uint64_t t0, uint64_t t1)
+uint64_t helper_stl_c_phys(uint64_t val, uint64_t addr)
{
uint64_t ret;
- if (t1 == env->lock) {
- stl_raw(t1, t0);
+ if (addr == env->lock) {
+ stl_phys(addr, val);
ret = 0;
} else
ret = 1;
@@ -1158,12 +1152,12 @@ uint64_t helper_stl_c_raw(uint64_t t0, uint64_t t1)
return ret;
}
-uint64_t helper_stq_c_raw(uint64_t t0, uint64_t t1)
+uint64_t helper_stq_c_phys(uint64_t val, uint64_t addr)
{
uint64_t ret;
- if (t1 == env->lock) {
- stq_raw(t1, t0);
+ if (addr == env->lock) {
+ stq_phys(addr, val);
ret = 0;
} else
ret = 1;
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index e9463ae..6936802 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -1794,19 +1794,19 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access (hw_ldl/p) */
- gen_helper_ldl_raw(cpu_ir[ra], addr);
+ gen_helper_ldl_phys(cpu_ir[ra], addr);
break;
case 0x1:
/* Quadword physical access (hw_ldq/p) */
- gen_helper_ldq_raw(cpu_ir[ra], addr);
+ gen_helper_ldq_phys(cpu_ir[ra], addr);
break;
case 0x2:
/* Longword physical access with lock (hw_ldl_l/p) */
- gen_helper_ldl_l_raw(cpu_ir[ra], addr);
+ gen_helper_ldl_l_phys(cpu_ir[ra], addr);
break;
case 0x3:
/* Quadword physical access with lock (hw_ldq_l/p) */
- gen_helper_ldq_l_raw(cpu_ir[ra], addr);
+ gen_helper_ldq_l_phys(cpu_ir[ra], addr);
break;
case 0x4:
/* Longword virtual PTE fetch (hw_ldl/v) */
@@ -1825,12 +1825,12 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
case 0x8:
/* Longword virtual access (hw_ldl) */
gen_helper_st_virt_to_phys(addr, addr);
- gen_helper_ldl_raw(cpu_ir[ra], addr);
+ gen_helper_ldl_phys(cpu_ir[ra], addr);
break;
case 0x9:
/* Quadword virtual access (hw_ldq) */
gen_helper_st_virt_to_phys(addr, addr);
- gen_helper_ldq_raw(cpu_ir[ra], addr);
+ gen_helper_ldq_phys(cpu_ir[ra], addr);
break;
case 0xA:
/* Longword virtual access with protection check (hw_ldl/w) */
@@ -1844,14 +1844,14 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
/* Longword virtual access with alt access mode (hw_ldl/a)*/
gen_helper_set_alt_mode();
gen_helper_st_virt_to_phys(addr, addr);
- gen_helper_ldl_raw(cpu_ir[ra], addr);
+ gen_helper_ldl_phys(cpu_ir[ra], addr);
gen_helper_restore_mode();
break;
case 0xD:
/* Quadword virtual access with alt access mode (hw_ldq/a) */
gen_helper_set_alt_mode();
gen_helper_st_virt_to_phys(addr, addr);
- gen_helper_ldq_raw(cpu_ir[ra], addr);
+ gen_helper_ldq_phys(cpu_ir[ra], addr);
gen_helper_restore_mode();
break;
case 0xE:
@@ -2123,29 +2123,29 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access */
- gen_helper_stl_raw(val, addr);
+ gen_helper_stl_phys(val, addr);
break;
case 0x1:
/* Quadword physical access */
- gen_helper_stq_raw(val, addr);
+ gen_helper_stq_phys(val, addr);
break;
case 0x2:
/* Longword physical access with lock */
- gen_helper_stl_c_raw(val, val, addr);
+ gen_helper_stl_c_phys(val, val, addr);
break;
case 0x3:
/* Quadword physical access with lock */
- gen_helper_stq_c_raw(val, val, addr);
+ gen_helper_stq_c_phys(val, val, addr);
break;
case 0x4:
/* Longword virtual access */
gen_helper_st_virt_to_phys(addr, addr);
- gen_helper_stl_raw(val, addr);
+ gen_helper_stl_phys(val, addr);
break;
case 0x5:
/* Quadword virtual access */
gen_helper_st_virt_to_phys(addr, addr);
- gen_helper_stq_raw(val, addr);
+ gen_helper_stq_phys(val, addr);
break;
case 0x6:
/* Invalid */
@@ -2169,14 +2169,14 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
/* Longword virtual access with alternate access mode */
gen_helper_set_alt_mode();
gen_helper_st_virt_to_phys(addr, addr);
- gen_helper_stl_raw(val, addr);
+ gen_helper_stl_phys(val, addr);
gen_helper_restore_mode();
break;
case 0xD:
/* Quadword virtual access with alternate access mode */
gen_helper_set_alt_mode();
gen_helper_st_virt_to_phys(addr, addr);
- gen_helper_stl_raw(val, addr);
+ gen_helper_stl_phys(val, addr);
gen_helper_restore_mode();
break;
case 0xE:
--
1.6.2
next prev parent reply other threads:[~2009-03-24 15:48 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-03-24 15:47 [Qemu-devel] [PATCH 0/25]: add alpha es40 system emulation (v3) Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 01/25] Add support for multi-level phys map Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 02/25] Fix bug: palcode is at least 6 bits Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 03/25] Fix bug: do not mask address LSBs for ldwu Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 04/25] Fix bug: integer conditionnal branch offset is 21 bits wide Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 05/25] bug fix: avoid nop to override next instruction Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 06/25] Fix temp free for hw_st Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 07/25] Increase Alpha physical address size to 44 bits Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 08/25] Alpha: set target page size to 13 bits Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 09/25] Allow 5 mmu indexes Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 10/25] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 11/25] Add square wave output support Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 12/25] Add ali1543 super IO pci device Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 13/25] Add 21272 chipset (memory and pci controller for alpha) Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 14/25] Add target-alpha/machine.c and hw/es40.c for es40 machine emulation Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 15/25] Move softmmu_helper.h from exec.h to op_helper.c on alpha Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 16/25] Document which IPR are used by 21264 Tristan Gingold
2009-03-24 15:47 ` [Qemu-devel] [PATCH 17/25] tb_flush helper should flush the tb (and not the tlb) Tristan Gingold
2009-03-24 15:48 ` [Qemu-devel] [PATCH 18/25] Add instruction name in comments for hw_ld opcode Tristan Gingold
2009-03-24 15:48 ` [Qemu-devel] [PATCH 19/25] Remove PALCODE_ declarations (unused) Tristan Gingold
2009-03-24 15:48 ` Tristan Gingold [this message]
2009-03-24 15:48 ` [Qemu-devel] [PATCH 21/25] Add alpha_cpu_list Tristan Gingold
2009-03-24 15:48 ` [Qemu-devel] [PATCH 22/25] Alpha: lower parent irq when irq is lowered Tristan Gingold
2009-03-24 15:48 ` [Qemu-devel] [PATCH 23/25] Move linux-user pal emulation to linux-user/ Tristan Gingold
2009-03-24 15:48 ` [Qemu-devel] [PATCH 24/25] Correctly decode hw_ld/hw_st opcodes for all alpha implementations Tristan Gingold
2009-03-24 15:48 ` [Qemu-devel] [PATCH 25/25] Add full emulation for 21264 Tristan Gingold
2009-03-24 23:00 ` [Qemu-devel] [PATCH 13/25] Add 21272 chipset (memory and pci controller for alpha) Robert Reif
2009-03-25 7:58 ` Tristan Gingold
2009-03-25 8:09 ` Tristan Gingold
2009-03-29 0:37 ` [Qemu-devel] [PATCH 09/25] Allow 5 mmu indexes Aurelien Jarno
2009-03-24 16:46 ` [Qemu-devel] [PATCH 01/25] Add support for multi-level phys map Paul Brook
2009-03-24 19:42 ` [Qemu-devel] [PATCH 0/25]: add alpha es40 system emulation (v3) Brian Wheeler
2009-03-25 7:37 ` Tristan Gingold
2009-03-25 12:43 ` Brian Wheeler
2009-03-25 12:53 ` Tristan Gingold
2009-03-29 0:14 ` Aurelien Jarno
2009-03-29 0:31 ` Aurelien Jarno
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