[Qemu-devel] [PATCH 0/10] tcg: improve logical op support for ppc hosts

[Qemu-devel] [PATCH 0/10] tcg: improve logical op support for ppc hosts

[Nathan Froyd]

This patch series implements the necessary support for native TCG
implementations the logical operations andc, orc, eqv, nor, and nand (as
opposed to the synthesized implementations currently used by TCG).  It
also implements backend support for said operations in the ppc and ppc64
backends.

I have tested it sparsely on a ppc64 machine I have access to; Linux
user-mode emulation seems to be broken on ppc hosts.  I could not run a
given binary (something as simple as ls or complicated as gcc) with
ppc{,64}-linux-user targeted QEMU.  Prior to the guest application
crashing, however, I could see in qemu.log that several
andc/orc/eqv/nand/nor instructions were being used and being translated
correctly.

The patch series also includes one bugfix at the very end, which removes
r0 from the allocation pool.  The logic of the patch seems
straightforward enough to me, but I confess to not being a TCG expert,
so if TCG somehow avoids generating instructions with r0 in the "wrong"
places, I'd be happy to hear of an explanation why.

-Nathan

[Qemu-devel] [PATCH 01/10] Add TCG ops for various logical operations

[Nathan Froyd]

 andc, orc, nor, nand, and eqv, to be precise.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-opc.h |   32 ++++++++++++++++++++++++++++++++
 1 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 3a095fc..e4e1ce4 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -67,6 +67,22 @@ DEF2(divu2_i32, 2, 3, 0, 0)
 DEF2(and_i32, 1, 2, 0, 0)
 DEF2(or_i32, 1, 2, 0, 0)
 DEF2(xor_i32, 1, 2, 0, 0)
+#ifdef TCG_TARGET_HAS_andc_i32
+DEF2(andc_i32, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_eqv_i32
+DEF2(eqv_i32, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_nand_i32
+DEF2(nand_i32, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_nor_i32
+DEF2(nor_i32, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_orc_i32
+DEF2(orc_i32, 1, 2, 0, 0)
+#endif
+
 /* shifts/rotates */
 DEF2(shl_i32, 1, 2, 0, 0)
 DEF2(shr_i32, 1, 2, 0, 0)
@@ -133,6 +149,22 @@ DEF2(divu2_i64, 2, 3, 0, 0)
 DEF2(and_i64, 1, 2, 0, 0)
 DEF2(or_i64, 1, 2, 0, 0)
 DEF2(xor_i64, 1, 2, 0, 0)
+#ifdef TCG_TARGET_HAS_andc_i64
+DEF2(andc_i64, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_eqv_i64
+DEF2(eqv_i64, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_nand_i64
+DEF2(nand_i64, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_nor_i64
+DEF2(nor_i64, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_orc_i64
+DEF2(orc_i64, 1, 2, 0, 0)
+#endif
+
 /* shifts/rotates */
 DEF2(shl_i64, 1, 2, 0, 0)
 DEF2(shr_i64, 1, 2, 0, 0)
-- 
1.6.0.5

[Qemu-devel] [PATCH 02/10] Specialize tcg_gen_not_i64 for 32-bit targets

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-op.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 645b908..2233170 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1515,6 +1515,9 @@ static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
 {
 #ifdef TCG_TARGET_HAS_not_i64
     tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
+#elif defined(TCG_TARGET_HAS_not_i32)
+    tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
+    tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
 #else
     tcg_gen_xori_i64(ret, arg, -1);
 #endif
-- 
1.6.0.5

Re: [Qemu-devel] [PATCH 02/10] Specialize tcg_gen_not_i64 for 32-bit targets

[Paul Brook]

>  #ifdef TCG_TARGET_HAS_not_i64
>      tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
> +#elif defined(TCG_TARGET_HAS_not_i32)
> +    tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
> +    tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
>  #else
>      tcg_gen_xori_i64(ret, arg, -1);

This is only valid when TCG_TARGET_REG_BITS == 32

Annother possibility is to move the the op_not generation to gen_xori. You 
should get this for free then.

Paul

[Qemu-devel] [PATCH 03/10] Implement specialized andc_i{32,64}

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-op.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 2233170..031bdf7 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1573,20 +1573,31 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 hi
 
 static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_andc_i32
+    tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
+#else
     TCGv_i32 t0;
     t0 = tcg_temp_new_i32();
     tcg_gen_not_i32(t0, arg2);
     tcg_gen_and_i32(ret, arg1, t0);
     tcg_temp_free_i32(t0);
+#endif
 }
 
 static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_andc_i64
+    tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_andc_i32)
+    tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     TCGv_i64 t0;
     t0 = tcg_temp_new_i64();
     tcg_gen_not_i64(t0, arg2);
     tcg_gen_and_i64(ret, arg1, t0);
     tcg_temp_free_i64(t0);
+#endif
 }
 
 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-- 
1.6.0.5

[Qemu-devel] [PATCH 04/10] Implement specialized eqv_{i32,i64}

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-op.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 031bdf7..aaf224b 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1602,14 +1602,25 @@ static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_eqv_i32
+    tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
+#else
     tcg_gen_xor_i32(ret, arg1, arg2);
     tcg_gen_not_i32(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_eqv_i64
+    tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_eqv_i32)
+    tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     tcg_gen_xor_i64(ret, arg1, arg2);
     tcg_gen_not_i64(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-- 
1.6.0.5

[Qemu-devel] [PATCH 05/10] Implement specialized nand_i{32,64}

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-op.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index aaf224b..aefaeb1 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1625,14 +1625,25 @@ static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_nand_i32
+    tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
+#else
     tcg_gen_and_i32(ret, arg1, arg2);
     tcg_gen_not_i32(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_nand_i64
+    tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_nand_i32)
+    tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     tcg_gen_and_i64(ret, arg1, arg2);
     tcg_gen_not_i64(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-- 
1.6.0.5

[Qemu-devel] [PATCH 06/10] Implement specialized nor_i{32,64}

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-op.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index aefaeb1..bc6dfb6 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1648,14 +1648,25 @@ static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_nor_i32
+    tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
+#else
     tcg_gen_or_i32(ret, arg1, arg2);
     tcg_gen_not_i32(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_nor_i64
+    tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_nor_i32)
+    tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     tcg_gen_or_i64(ret, arg1, arg2);
     tcg_gen_not_i64(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-- 
1.6.0.5

[Qemu-devel] [PATCH 07/10] Implement specialized orc_i{32,64}

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-op.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index bc6dfb6..9c51636 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1671,20 +1671,31 @@ static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_orc_i32
+    tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
+#else
     TCGv_i32 t0;
     t0 = tcg_temp_new_i32();
     tcg_gen_not_i32(t0, arg2);
     tcg_gen_or_i32(ret, arg1, t0);
     tcg_temp_free_i32(t0);
+#endif
 }
 
 static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_orc_i64
+    tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_orc_i32)
+    tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     TCGv_i64 t0;
     t0 = tcg_temp_new_i64();
     tcg_gen_not_i64(t0, arg2);
     tcg_gen_or_i64(ret, arg1, t0);
     tcg_temp_free_i64(t0);
+#endif
 }
 
 static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-- 
1.6.0.5

[Qemu-devel] [PATCH 08/10] Implement new logical instructions for ppc

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/ppc/tcg-target.c |   26 ++++++++++++++++++++++++++
 tcg/ppc/tcg-target.h |    5 +++++
 2 files changed, 31 insertions(+), 0 deletions(-)

diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 23f94a8..bdab71d 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -335,6 +335,11 @@ static int tcg_target_const_match(tcg_target_long val,
 
 #define EXTSB  XO31(954)
 #define EXTSH  XO31(922)
+#define NAND   XO31(476)
+#define NOR    XO31(124)
+#define EQV    XO31(284)
+#define ANDC   XO31( 60)
+#define ORC    XO31(412)
 #define ADD    XO31(266)
 #define ADDE   XO31(138)
 #define ADDC   XO31( 10)
@@ -1267,6 +1272,22 @@ static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
             tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
         break;
 
+    case INDEX_op_andc_i32:
+        tcg_out32 (s, ANDC | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_eqv_i32:
+        tcg_out32 (s, EQV | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_nand_i32:
+        tcg_out32 (s, NAND | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_nor_i32:
+        tcg_out32 (s, NOR | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_orc_i32:
+        tcg_out32 (s, ORC | SAB (args[0], args[1], args[2]));
+        break;
+
     case INDEX_op_mul_i32:
         if (const_args[2]) {
             if (args[2] == (int16_t) args[2])
@@ -1462,6 +1483,11 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_and_i32, { "r", "r", "ri" } },
     { INDEX_op_or_i32, { "r", "r", "ri" } },
     { INDEX_op_xor_i32, { "r", "r", "ri" } },
+    { INDEX_op_andc_i32, { "r", "r", "r" } },
+    { INDEX_op_eqv_i32, { "r", "r", "r" } },
+    { INDEX_op_nand_i32, { "r", "r", "r" } },
+    { INDEX_op_nor_i32, { "r", "r", "r" } },
+    { INDEX_op_orc_i32, { "r", "r", "r" } },
 
     { INDEX_op_shl_i32, { "r", "r", "ri" } },
     { INDEX_op_shr_i32, { "r", "r", "ri" } },
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 5faf730..385f0ff 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -81,6 +81,11 @@ enum {
 #define TCG_TARGET_HAS_div_i32
 #define TCG_TARGET_HAS_ext8s_i32
 #define TCG_TARGET_HAS_ext16s_i32
+#define TCG_TARGET_HAS_andc_i32
+#define TCG_TARGET_HAS_eqv_i32
+#define TCG_TARGET_HAS_nand_i32
+#define TCG_TARGET_HAS_nor_i32
+#define TCG_TARGET_HAS_orc_i32
 
 #define TCG_AREG0 TCG_REG_R27
 #define TCG_AREG1 TCG_REG_R24
-- 
1.6.0.5

[Qemu-devel] [PATCH 09/10] Implement new logical instructions for ppc64

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/ppc64/tcg-target.c |   36 ++++++++++++++++++++++++++++++++++++
 tcg/ppc64/tcg-target.h |   10 ++++++++++
 2 files changed, 46 insertions(+), 0 deletions(-)

diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index a96314c..fc8beba 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -322,6 +322,11 @@ static int tcg_target_const_match (tcg_target_long val,
 #define EXTSB  XO31(954)
 #define EXTSH  XO31(922)
 #define EXTSW  XO31(986)
+#define NAND   XO31(476)
+#define NOR    XO31(124)
+#define EQV    XO31(284)
+#define ANDC   XO31( 60)
+#define ORC    XO31(412)
 #define ADD    XO31(266)
 #define ADDE   XO31(138)
 #define ADDC   XO31( 10)
@@ -1196,6 +1201,27 @@ static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
             tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
         break;
 
+    case INDEX_op_andc_i32:
+    case INDEX_op_andc_i64:
+        tcg_out32 (s, ANDC | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_eqv_i32:
+    case INDEX_op_eqv_i64:
+        tcg_out32 (s, EQV | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_nand_i32:
+    case INDEX_op_nand_i64:
+        tcg_out32 (s, NAND | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_nor_i32:
+    case INDEX_op_nor_i64:
+        tcg_out32 (s, NOR | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_orc_i32:
+    case INDEX_op_orc_i64:
+        tcg_out32 (s, ORC | SAB (args[0], args[1], args[2]));
+        break;
+
     case INDEX_op_mul_i32:
         if (const_args[2]) {
             if (args[2] == (int16_t) args[2])
@@ -1431,6 +1457,11 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_and_i32, { "r", "r", "ri" } },
     { INDEX_op_or_i32, { "r", "r", "ri" } },
     { INDEX_op_xor_i32, { "r", "r", "ri" } },
+    { INDEX_op_andc_i32, { "r", "r", "r" } },
+    { INDEX_op_eqv_i32, { "r", "r", "r" } },
+    { INDEX_op_nand_i32, { "r", "r", "r" } },
+    { INDEX_op_nor_i32, { "r", "r", "r" } },
+    { INDEX_op_orc_i32, { "r", "r", "r" } },
 
     { INDEX_op_shl_i32, { "r", "r", "ri" } },
     { INDEX_op_shr_i32, { "r", "r", "ri" } },
@@ -1446,6 +1477,11 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_and_i64, { "r", "r", "rZ" } },
     { INDEX_op_or_i64, { "r", "r", "rZ" } },
     { INDEX_op_xor_i64, { "r", "r", "rZ" } },
+    { INDEX_op_andc_i64, { "r", "r", "r" } },
+    { INDEX_op_eqv_i64, { "r", "r", "r" } },
+    { INDEX_op_nand_i64, { "r", "r", "r" } },
+    { INDEX_op_nor_i64, { "r", "r", "r" } },
+    { INDEX_op_orc_i64, { "r", "r", "r" } },
 
     { INDEX_op_shl_i64, { "r", "r", "ri" } },
     { INDEX_op_shr_i64, { "r", "r", "ri" } },
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 452bfda..f0a4206 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -77,6 +77,16 @@ enum {
 #define TCG_TARGET_HAS_ext8s_i64
 #define TCG_TARGET_HAS_ext16s_i64
 #define TCG_TARGET_HAS_ext32s_i64
+#define TCG_TARGET_HAS_andc_i32
+#define TCG_TARGET_HAS_eqv_i32
+#define TCG_TARGET_HAS_nand_i32
+#define TCG_TARGET_HAS_nor_i32
+#define TCG_TARGET_HAS_orc_i32
+#define TCG_TARGET_HAS_andc_i64
+#define TCG_TARGET_HAS_eqv_i64
+#define TCG_TARGET_HAS_nand_i64
+#define TCG_TARGET_HAS_nor_i64
+#define TCG_TARGET_HAS_orc_i64
 
 #define TCG_AREG0 TCG_REG_R27
 #define TCG_AREG1 TCG_REG_R24
-- 
1.6.0.5

[Qemu-devel] [PATCH 10/10] Remove r0 from the allocation pool on ppc/ppc64

[Nathan Froyd]

r0 is used as a temporary for forming 32-bit constants; it also has
unexpected behavior when used as a base register in load and store
instructions.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/ppc/tcg-target.c   |    1 -
 tcg/ppc64/tcg-target.c |    1 -
 2 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index bdab71d..086c52e 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -112,7 +112,6 @@ static const int tcg_target_reg_alloc_order[] = {
 #ifndef __linux__
     TCG_REG_R13,
 #endif
-    TCG_REG_R0,
     TCG_REG_R1,
     TCG_REG_R2,
     TCG_REG_R24,
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index fc8beba..952d757 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -105,7 +105,6 @@ static const int tcg_target_reg_alloc_order[] = {
     TCG_REG_R11,
     TCG_REG_R12,
     TCG_REG_R13,
-    TCG_REG_R0,
     TCG_REG_R1,
     TCG_REG_R2,
     TCG_REG_R24,
-- 
1.6.0.5

Re: [Qemu-devel] [PATCH 10/10] Remove r0 from the allocation pool on ppc/ppc64

[malc]

On Sat, 28 Mar 2009, Nathan Froyd wrote:

> r0 is used as a temporary for forming 32-bit constants; it also has
> unexpected behavior when used as a base register in load and store
> instructions.

R0 is marked reserved in tcg_target_init, so this change shouldn't
actually affect anything...

-- 
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Re: [Qemu-devel] [PATCH 0/10] tcg: improve logical op support for ppc hosts

[malc]

On Sat, 28 Mar 2009, Nathan Froyd wrote:

> This patch series implements the necessary support for native TCG
> implementations the logical operations andc, orc, eqv, nor, and nand (as
> opposed to the synthesized implementations currently used by TCG).  It
> also implements backend support for said operations in the ppc and ppc64
> backends.
> 
> I have tested it sparsely on a ppc64 machine I have access to; Linux
> user-mode emulation seems to be broken on ppc hosts.  I could not run a
> given binary (something as simple as ls or complicated as gcc) with
> ppc{,64}-linux-user targeted QEMU.  Prior to the guest application
> crashing, however, I could see in qemu.log that several
> andc/orc/eqv/nand/nor instructions were being used and being translated
> correctly.

Hmm.. ls works, gcc dies with:

gcc: /usr/lib/gcc/powerpc-slackware-linux/3.4.6/specs: Value too large for 
defined data type

I know that some frame setup logic is missing but the core (translatio/tcg)
should be fine.

> The patch series also includes one bugfix at the very end, which removes
> r0 from the allocation pool.  The logic of the patch seems
> straightforward enough to me, but I confess to not being a TCG expert,
> so if TCG somehow avoids generating instructions with r0 in the "wrong"
> places, I'd be happy to hear of an explanation why.
> 
> -Nathan
> 
> 

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