From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lng6k-0003jR-Jo for qemu-devel@nongnu.org; Sat, 28 Mar 2009 17:30:26 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lng6f-0003ep-6b for qemu-devel@nongnu.org; Sat, 28 Mar 2009 17:30:25 -0400 Received: from [199.232.76.173] (port=53570 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lng6f-0003ec-1H for qemu-devel@nongnu.org; Sat, 28 Mar 2009 17:30:21 -0400 Received: from mx20.gnu.org ([199.232.41.8]:8426) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Lng6e-0004oE-Mq for qemu-devel@nongnu.org; Sat, 28 Mar 2009 17:30:20 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Lng6e-0004ap-0G for qemu-devel@nongnu.org; Sat, 28 Mar 2009 17:30:20 -0400 From: Nathan Froyd Date: Sat, 28 Mar 2009 14:30:17 -0700 Message-Id: <1238275817-9758-5-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1238275817-9758-1-git-send-email-froydnj@codesourcery.com> References: <1238275817-9758-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 4/4] create TCG slots for registers based on CPU Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org There's no point in creating floating-point registers if the chip we're emulating doesn't have them. Likewise for Altivec and SPE registers. Signed-off-by: Nathan Froyd --- target-ppc/translate.c | 52 +++++++++++++++++++++++++++-------------------- 1 files changed, 30 insertions(+), 22 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 412c8d0..8170718 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -104,36 +104,42 @@ void ppc_translate_init(const ppc_def_t *def) offsetof(CPUState, gpr[i]), p); p += (i < 10) ? 3 : 4; #if !defined(TARGET_PPC64) - sprintf(p, "r%dH", i); - cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, gprh[i]), p); - p += (i < 10) ? 4 : 5; + if (def->insns_flags & PPC_SPE) { + sprintf(p, "r%dH", i); + cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, gprh[i]), p); + p += (i < 10) ? 4 : 5; + } #endif - sprintf(p, "fp%d", i); - cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, fpr[i]), p); - p += (i < 10) ? 4 : 5; + if (def->insns_flags & PPC_FLOAT) { + sprintf(p, "fp%d", i); + cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, + offsetof(CPUState, fpr[i]), p); + p += (i < 10) ? 4 : 5; + } - sprintf(p, "avr%dH", i); + if (def->insns_flags & PPC_ALTIVEC) { + sprintf(p, "avr%dH", i); #ifdef WORDS_BIGENDIAN - cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, avr[i].u64[0]), p); + cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, + offsetof(CPUState, avr[i].u64[0]), p); #else - cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, avr[i].u64[1]), p); + cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, + offsetof(CPUState, avr[i].u64[1]), p); #endif - p += (i < 10) ? 6 : 7; + p += (i < 10) ? 6 : 7; - sprintf(p, "avr%dL", i); + sprintf(p, "avr%dL", i); #ifdef WORDS_BIGENDIAN - cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, avr[i].u64[1]), p); + cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, + offsetof(CPUState, avr[i].u64[1]), p); #else - cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUState, avr[i].u64[0]), p); + cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, + offsetof(CPUState, avr[i].u64[0]), p); #endif - p += (i < 10) ? 6 : 7; + p += (i < 10) ? 6 : 7; + } } cpu_nip = tcg_global_mem_new(TCG_AREG0, @@ -154,8 +160,10 @@ void ppc_translate_init(const ppc_def_t *def) cpu_reserve = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, reserve), "reserve"); - cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, fpscr), "fpscr"); + if (def->insns_flags & PPC_FLOAT) { + cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, fpscr), "fpscr"); + } cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, access_type), "access_type"); -- 1.6.0.5