From: Brian Wheeler <bdwheele@indiana.edu>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 0/20]: add alpha es40 system emulation (v4)
Date: Mon, 30 Mar 2009 12:43:35 -0400 [thread overview]
Message-ID: <1238431415.2272.18.camel@nibbler.dlib.indiana.edu> (raw)
In-Reply-To: <B6DF07F1-4A1C-443B-8F48-211A930C851A@adacore.com>
[-- Attachment #1: Type: text/plain, Size: 564 bytes --]
On Mon, 2009-03-30 at 18:04 +0200, Tristan Gingold wrote:
> On Mar 30, 2009, at 5:46 PM, Brian Wheeler wrote:
>
> > I get a fatal message on boot:
> >
> > es40: arr[0]=0000000000004005: 128MB at 128MB
> > qemu: fatal: cpu_alpha_mtpr_21264: ipr 0x80 not handled
> >
> >
> > Putting an empty case in helper.c gets past that, but then fails on
> > 0xf0
> > and 0x22. Then it fails on pctx.astrr
>
> Looks like garbage is executed. Can you send to me /tmp/qemu.log when
> run with -d in_asm,cpu,exec ?
>
> Thanks,
> Tristan.
>
>
>
Its attached.
Brian
[-- Attachment #2: qemu.log --]
[-- Type: text/x-log, Size: 7688 bytes --]
pc 0000000000008000 mem_idx 0
opcode 47ff0410 2
opc 11 ra 31 rb 31 rc 16 disp16 0410
pc 0000000000008004 mem_idx 0
opcode c3402e1e 4
opc 30 ra 26 rb 0 rc 30 disp16 2e1e
PC 0000000000008000 pal=1
IR00 v0 0000000000000000 IR01 t0 0000000000000000 IR02 t1 0000000000000000
IR03 t2 0000000000000000 IR04 t3 0000000000000000 IR05 t4 0000000000000000
IR06 t5 0000000000000000 IR07 t6 0000000000000000 IR08 t7 0000000000000000
IR09 s0 0000000000000000 IR10 s1 0000000000000000 IR11 s2 0000000000000000
IR12 s3 0000000000000000 IR13 s4 0000000000000000 IR14 s5 0000000000000000
IR15 fp 0000000000000000 IR16 a0 0000000000000000 IR17 a1 0000000000000000
IR18 a2 0000000000000000 IR19 a3 0000000000000000 IR20 a4 0000000000000000
IR21 a5 0000000000000000 IR22 t8 0000000000000000 IR23 t9 0000000000000000
IR24 t10 0000000000000000 IR25 t11 0000000000000000 IR26 ra 0000000000000000
IR27 t12 0000000000000000 IR28 at 0000000000000000 IR29 gp 0000000000000000
IR30 sp 0000000000000000
FIR00 0000000000000000 FIR01 0000000000000000 FIR02 0000000000000000
FIR03 0000000000000000 FIR04 0000000000000000 FIR05 0000000000000000
FIR06 0000000000000000 FIR07 0000000000000000 FIR08 0000000000000000
FIR09 0000000000000000 FIR10 0000000000000000 FIR11 0000000000000000
FIR12 0000000000000000 FIR13 0000000000000000 FIR14 0000000000000000
FIR15 0000000000000000 FIR16 0000000000000000 FIR17 0000000000000000
FIR18 0000000000000000 FIR19 0000000000000000 FIR20 0000000000000000
FIR21 0000000000000000 FIR22 0000000000000000 FIR23 0000000000000000
FIR24 0000000000000000 FIR25 0000000000000000 FIR26 0000000000000000
FIR27 0000000000000000 FIR28 0000000000000000 FIR29 0000000000000000
FIR30 0000000000000000
IN:
0x0000000000008000: clr a0
0x0000000000008004: br ra,0x13880
pc 0000000000013880 mem_idx 0
opcode 44000400 6
opc 11 ra 0 rb 0 rc 0 disp16 0400
pc 0000000000013884 mem_idx 0
opcode 47ff041f 8
opc 11 ra 31 rb 31 rc 31 disp16 041f
pc 0000000000013888 mem_idx 0
opcode 47ff041f 10
opc 11 ra 31 rb 31 rc 31 disp16 041f
pc 000000000001388c mem_idx 0
opcode 47ff041f 12
opc 11 ra 31 rb 31 rc 31 disp16 041f
pc 0000000000013890 mem_idx 0
opcode 77ff0310 14
opc 1d ra 31 rb 31 rc 16 disp16 0310
PC 0000000000013880 pal=1
IR00 v0 0000000000000000 IR01 t0 0000000000000000 IR02 t1 0000000000000000
IR03 t2 0000000000000000 IR04 t3 0000000000000000 IR05 t4 0000000000000000
IR06 t5 0000000000000000 IR07 t6 0000000000000000 IR08 t7 0000000000000000
IR09 s0 0000000000000000 IR10 s1 0000000000000000 IR11 s2 0000000000000000
IR12 s3 0000000000000000 IR13 s4 0000000000000000 IR14 s5 0000000000000000
IR15 fp 0000000000000000 IR16 a0 0000000000000000 IR17 a1 0000000000000000
IR18 a2 0000000000000000 IR19 a3 0000000000000000 IR20 a4 0000000000000000
IR21 a5 0000000000000000 IR22 t8 0000000000000000 IR23 t9 0000000000000000
IR24 t10 0000000000000000 IR25 t11 0000000000000000 IR26 ra 0000000000008008
IR27 t12 0000000000000000 IR28 at 0000000000000000 IR29 gp 0000000000000000
IR30 sp 0000000000000000
FIR00 0000000000000000 FIR01 0000000000000000 FIR02 0000000000000000
FIR03 0000000000000000 FIR04 0000000000000000 FIR05 0000000000000000
FIR06 0000000000000000 FIR07 0000000000000000 FIR08 0000000000000000
FIR09 0000000000000000 FIR10 0000000000000000 FIR11 0000000000000000
FIR12 0000000000000000 FIR13 0000000000000000 FIR14 0000000000000000
FIR15 0000000000000000 FIR16 0000000000000000 FIR17 0000000000000000
FIR18 0000000000000000 FIR19 0000000000000000 FIR20 0000000000000000
FIR21 0000000000000000 FIR22 0000000000000000 FIR23 0000000000000000
FIR24 0000000000000000 FIR25 0000000000000000 FIR26 0000000000000000
FIR27 0000000000000000 FIR28 0000000000000000 FIR29 0000000000000000
FIR30 0000000000000000
IN:
0x0000000000013880: mov v0,v0
0x0000000000013884: nop
0x0000000000013888: nop
0x000000000001388c: nop
0x0000000000013890: pal1d 0x3ff0310
pc 0000000000013894 mem_idx 0
opcode 77ffa380 16
opc 1d ra 31 rb 31 rc 0 disp16 ffffa380
PC 0000000000013894 pal=1
IR00 v0 0000000000000000 IR01 t0 0000000000000000 IR02 t1 0000000000000000
IR03 t2 0000000000000000 IR04 t3 0000000000000000 IR05 t4 0000000000000000
IR06 t5 0000000000000000 IR07 t6 0000000000000000 IR08 t7 0000000000000000
IR09 s0 0000000000000000 IR10 s1 0000000000000000 IR11 s2 0000000000000000
IR12 s3 0000000000000000 IR13 s4 0000000000000000 IR14 s5 0000000000000000
IR15 fp 0000000000000000 IR16 a0 0000000000000000 IR17 a1 0000000000000000
IR18 a2 0000000000000000 IR19 a3 0000000000000000 IR20 a4 0000000000000000
IR21 a5 0000000000000000 IR22 t8 0000000000000000 IR23 t9 0000000000000000
IR24 t10 0000000000000000 IR25 t11 0000000000000000 IR26 ra 0000000000008008
IR27 t12 0000000000000000 IR28 at 0000000000000000 IR29 gp 0000000000000000
IR30 sp 0000000000000000
FIR00 0000000000000000 FIR01 0000000000000000 FIR02 0000000000000000
FIR03 0000000000000000 FIR04 0000000000000000 FIR05 0000000000000000
FIR06 0000000000000000 FIR07 0000000000000000 FIR08 0000000000000000
FIR09 0000000000000000 FIR10 0000000000000000 FIR11 0000000000000000
FIR12 0000000000000000 FIR13 0000000000000000 FIR14 0000000000000000
FIR15 0000000000000000 FIR16 0000000000000000 FIR17 0000000000000000
FIR18 0000000000000000 FIR19 0000000000000000 FIR20 0000000000000000
FIR21 0000000000000000 FIR22 0000000000000000 FIR23 0000000000000000
FIR24 0000000000000000 FIR25 0000000000000000 FIR26 0000000000000000
FIR27 0000000000000000 FIR28 0000000000000000 FIR29 0000000000000000
FIR30 0000000000000000
IN:
0x0000000000013894: pal1d 0x3ffa380
qemu: fatal: cpu_alpha_mtpr_21264: ipr 0x80 not handled
PC 0000000000013894 pal=1
IR00 v0 0000000000000000 IR01 t0 0000000000000000 IR02 t1 0000000000000000
IR03 t2 0000000000000000 IR04 t3 0000000000000000 IR05 t4 0000000000000000
IR06 t5 0000000000000000 IR07 t6 0000000000000000 IR08 t7 0000000000000000
IR09 s0 0000000000000000 IR10 s1 0000000000000000 IR11 s2 0000000000000000
IR12 s3 0000000000000000 IR13 s4 0000000000000000 IR14 s5 0000000000000000
IR15 fp 0000000000000000 IR16 a0 0000000000000000 IR17 a1 0000000000000000
IR18 a2 0000000000000000 IR19 a3 0000000000000000 IR20 a4 0000000000000000
IR21 a5 0000000000000000 IR22 t8 0000000000000000 IR23 t9 0000000000000000
IR24 t10 0000000000000000 IR25 t11 0000000000000000 IR26 ra 0000000000008008
IR27 t12 0000000000000000 IR28 at 0000000000000000 IR29 gp 0000000000000000
IR30 sp 0000000000000000
FIR00 0000000000000000 FIR01 0000000000000000 FIR02 0000000000000000
FIR03 0000000000000000 FIR04 0000000000000000 FIR05 0000000000000000
FIR06 0000000000000000 FIR07 0000000000000000 FIR08 0000000000000000
FIR09 0000000000000000 FIR10 0000000000000000 FIR11 0000000000000000
FIR12 0000000000000000 FIR13 0000000000000000 FIR14 0000000000000000
FIR15 0000000000000000 FIR16 0000000000000000 FIR17 0000000000000000
FIR18 0000000000000000 FIR19 0000000000000000 FIR20 0000000000000000
FIR21 0000000000000000 FIR22 0000000000000000 FIR23 0000000000000000
FIR24 0000000000000000 FIR25 0000000000000000 FIR26 0000000000000000
FIR27 0000000000000000 FIR28 0000000000000000 FIR29 0000000000000000
FIR30 0000000000000000
prev parent reply other threads:[~2009-03-30 16:43 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-03-30 14:36 [Qemu-devel] [PATCH 0/20]: add alpha es40 system emulation (v4) Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 01/19] Add support for multi-level phys map Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 02/19] Increase Alpha physical address size to 44 bits Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 03/19] Alpha: set target page size to 13 bits Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 04/19] Allow 5 mmu indexes Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 05/19] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 06/19] Bug fix alpha: stop translation if too long Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 07/19] Alpha bug: fix palcode mask for user pal calls Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 08/19] Alpha: document more registers used by 21264 Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 09/19] Add square wave output support Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 10/19] Add ali1543 super IO pci device Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 11/19] Add 21272 chipset (memory and pci controller for alpha) Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 12/19] Add target-alpha/machine.c and hw/es40.c for es40 machine emulation Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 13/19] Move softmmu_helper.h from exec.h to op_helper.c on alpha Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 14/19] alpha ld helpers now directly return the value Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 15/19] Add alpha_cpu_list Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 16/19] Alpha: lower parent irq when irq is lowered Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 17/19] Move linux-user pal emulation to linux-user/ Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 18/19] Correctly decode hw_ld/hw_st opcodes for all alpha implementations Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 19/19] Add full emulation for 21264 Tristan Gingold
2009-04-07 21:52 ` [Qemu-devel] [PATCH 18/19] Correctly decode hw_ld/hw_st opcodes for all alpha implementations Aurelien Jarno
2009-04-08 12:26 ` Tristan Gingold
2009-04-15 14:42 ` [Qemu-devel] [PATCH 16/19] Alpha: lower parent irq when irq is lowered Aurelien Jarno
2009-04-07 22:29 ` [Qemu-devel] [PATCH 09/19] Add square wave output support Aurelien Jarno
2009-04-07 22:32 ` [Qemu-devel] [PATCH 08/19] Alpha: document more registers used by 21264 Aurelien Jarno
2009-04-07 22:31 ` [Qemu-devel] [PATCH 07/19] Alpha bug: fix palcode mask for user pal calls Aurelien Jarno
2009-04-07 21:44 ` [Qemu-devel] [PATCH 06/19] Bug fix alpha: stop translation if too long Aurelien Jarno
2009-04-15 14:30 ` [Qemu-devel] [PATCH 05/19] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code Aurelien Jarno
2009-04-21 12:10 ` Tristan Gingold
2009-04-07 21:48 ` [Qemu-devel] [PATCH 04/19] Allow 5 mmu indexes Aurelien Jarno
2009-04-07 21:47 ` [Qemu-devel] [PATCH 03/19] Alpha: set target page size to 13 bits Aurelien Jarno
2009-04-15 16:23 ` [Qemu-devel] [PATCH 01/19] Add support for multi-level phys map Aurelien Jarno
2009-04-21 12:11 ` Tristan Gingold
2009-03-30 15:46 ` [Qemu-devel] [PATCH 0/20]: add alpha es40 system emulation (v4) Brian Wheeler
2009-03-30 16:04 ` Tristan Gingold
2009-03-30 16:43 ` Brian Wheeler [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1238431415.2272.18.camel@nibbler.dlib.indiana.edu \
--to=bdwheele@indiana.edu \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).