From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LplAE-00031f-7S for qemu-devel@nongnu.org; Fri, 03 Apr 2009 11:18:38 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LplA9-0002zE-K2 for qemu-devel@nongnu.org; Fri, 03 Apr 2009 11:18:37 -0400 Received: from [199.232.76.173] (port=56556 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LplA9-0002zB-D4 for qemu-devel@nongnu.org; Fri, 03 Apr 2009 11:18:33 -0400 Received: from hartman.uits.indiana.edu ([129.79.1.194]:50520) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LplA9-0005BX-3E for qemu-devel@nongnu.org; Fri, 03 Apr 2009 11:18:33 -0400 Subject: Re: [Qemu-devel] PATCH/RFC: PCI memory mapping From: Brian Wheeler In-Reply-To: <200904022340.35427.paul@codesourcery.com> References: <1238684238.18745.17.camel@nibbler.dlib.indiana.edu> <200904022340.35427.paul@codesourcery.com> Content-Type: text/plain Date: Fri, 03 Apr 2009 11:05:49 -0400 Message-Id: <1238771149.28860.75.camel@nibbler.dlib.indiana.edu> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paul Brook Cc: qemu-devel@nongnu.org On Thu, 2009-04-02 at 22:40 +0000, Paul Brook wrote: > On Thursday 02 April 2009, Brian Wheeler wrote: > > [first off, if there's an easier way to do this, let me know!] > > > > This patch adds an address mapping function to the PCI bus so the host > > chipset can remap PCI generated addresses to the appropriate physical > > addresses. > > This should be integrated with the DMA APIs. Individual devices must not need > to be aware of bus bridges. All remapping should be handled by the DMA > routines. In principle there's no reason for this to be specific to PCI. > SPARC machines already have an IOMMU, so you should make sure your solution > also covers those systems. > > I recommend looking back in the list archives, there have been several > discussions about the requirements for bus address mapping. > > Paul I've been looking around the archives and I'm not finding what I'm looking for...though it may be that words like dma, address, etc are terribly generic in this context. I've found a few promising patches in the archives, but they don't seem to be in the code. Here's the problem I'm trying to solve: The alpha has an IOMMU which translates pci addresses to addresses which are used by the system. The first mapping is for local connect addresses which work out to: (0x80000000000ULL | (bus * 0x200000000ULL) | address Another mapping uses scatter-gather. A third one uses a direct connect mapping which is a base/range => new address mapping. My question is: where/how do I hook my function to translate the address from cpu_physical_memory_{register,read,write}() as called by the different devices into the addresses that I need? So, for example, a cirrus vga device on bus 1 when calling: cpu_register_physical_memory(addr, s->vram_size, s->cirrus_linear_io_addr); The address actually gets mapped to the alpha's address 0x80200000000 + addr? How do other architectures do this? Looking around the source, I'm not finding anything that stands out.... Thanks, and sorry for the newbie questions! Brian