From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LqoPN-0000Xo-JR for qemu-devel@nongnu.org; Mon, 06 Apr 2009 08:58:37 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LqoPG-0000Q0-4b for qemu-devel@nongnu.org; Mon, 06 Apr 2009 08:58:34 -0400 Received: from [199.232.76.173] (port=55325 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LqoPF-0000Pk-Vs for qemu-devel@nongnu.org; Mon, 06 Apr 2009 08:58:30 -0400 Received: from hartman.uits.indiana.edu ([129.79.1.194]:39870) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LqoPF-0007xc-Gw for qemu-devel@nongnu.org; Mon, 06 Apr 2009 08:58:29 -0400 Received: from mail-relay.iu.edu (candy.uits.indiana.edu [129.79.1.201]) by hartman.uits.indiana.edu (8.14.2/8.13.8/IU Messaging Team) with ESMTP id n36CwP2T006161 for ; Mon, 6 Apr 2009 08:58:25 -0400 Received: from [129.79.35.119] (nibbler.dlib.indiana.edu [129.79.35.119]) (authenticated bits=0) by mail-relay.iu.edu (8.14.2/8.13.8/IU Messaging Team Submission) with ESMTP id n36CwOWh015852 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 6 Apr 2009 08:58:25 -0400 From: Brian Wheeler Content-Type: text/plain Date: Mon, 06 Apr 2009 08:58:23 -0400 Message-Id: <1239022704.1975.18.camel@nibbler.dlib.indiana.edu> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 1/1] PCI Memory Mapping Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This patch * modifies pci_to_cpu_addr() to support device-bus location mapping * adds pci_register_physical_memory and pci_register_physical_memory_offset * modifies cirrus_vga to use pci_register_physical_memory The problem comes in with the alpha_softmmu target: pci_mem_base isn't a static offset. On the alpha the base is defined as: (0x80000000000ULL | (pci_dev->bus->bus_num * 0x200000000ULL) | addr So, when a device is put into the system, its pci_mem_base address depends on which bus it is put into. This patch only handles cpu->pci memory access. It doesn't do anything with DMA operations by the device. I'd really like some feedback on this, since its pretty important for the alpha_softmmu target. Thanks! Brian Signed-off-by: Brian Wheeler --------------- Index: hw/cirrus_vga.c =================================================================== --- hw/cirrus_vga.c (revision 7006) +++ hw/cirrus_vga.c (working copy) @@ -3327,9 +3327,9 @@ vga_dirty_log_stop((VGAState *)s); /* XXX: add byte swapping apertures */ - cpu_register_physical_memory(addr, s->vram_size, + pci_register_physical_memory(d, addr, s->vram_size, s->cirrus_linear_io_addr); - cpu_register_physical_memory(addr + 0x1000000, 0x400000, + pci_register_physical_memory(d, addr + 0x1000000, 0x400000, s->cirrus_linear_bitblt_io_addr); s->map_addr = s->map_end = 0; Index: hw/pci.c =================================================================== --- hw/pci.c (revision 7006) +++ hw/pci.c (working copy) @@ -273,11 +273,29 @@ return pci_dev; } -static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr) +static target_phys_addr_t pci_to_cpu_addr(PCIDevice *pci_dev, + target_phys_addr_t addr) { +#ifdef TARGET_ALPHA + return (0x80000000000ULL | (pci_dev->bus->bus_num * 0x200000000ULL) | addr; +#else return addr + pci_mem_base; +#endif } + +void pci_register_physical_memory_offset(PCIDevice *pci_dev, + target_phys_addr_t start_addr, + ram_addr_t size, + ram_addr_t phys_offset, + ram_addr_t region_offset) +{ + start_addr = pci_to_cpu_addr(pci_dev, start_addr); + cpu_register_physical_memory_offset(start_addr, size, phys_offset, + region_offset); +} + + static void pci_unregister_io_regions(PCIDevice *pci_dev) { PCIIORegion *r; @@ -290,7 +308,7 @@ if (r->type == PCI_ADDRESS_SPACE_IO) { isa_unassign_ioport(r->addr, r->size); } else { - cpu_register_physical_memory(pci_to_cpu_addr(r->addr), + cpu_register_physical_memory(pci_to_cpu_addr(pci_dev, r->addr), r->size, IO_MEM_UNASSIGNED); } @@ -409,7 +427,8 @@ isa_unassign_ioport(r->addr, r->size); } } else { - cpu_register_physical_memory(pci_to_cpu_addr(r->addr), + cpu_register_physical_memory(pci_to_cpu_addr(d, + r->addr), r->size, IO_MEM_UNASSIGNED); qemu_unregister_coalesced_mmio(r->addr, r->size); Index: hw/pci.h =================================================================== --- hw/pci.h (revision 7006) +++ hw/pci.h (working copy) @@ -213,6 +213,25 @@ cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val); } + + +void pci_register_physical_memory_offset(PCIDevice *pci_dev, + target_phys_addr_t start_addr, + ram_addr_t size, + ram_addr_t phys_offset, + ram_addr_t region_offset); +static inline void pci_register_physical_memory(PCIDevice *pci_dev, + target_phys_addr_t start_addr, + ram_addr_t size, + ram_addr_t phys_offset) +{ + pci_register_physical_memory_offset(pci_dev, start_addr, size, + phys_offset, 0); +} + + + + /* lsi53c895a.c */ #define LSI_MAX_DEVS 7 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);