[Qemu-devel] [PATCH 9/9] Implement new logical instructions for ppc64

[Nathan Froyd <froydnj@codesourcery.com>]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/ppc64/tcg-target.c |   36 ++++++++++++++++++++++++++++++++++++
 tcg/ppc64/tcg-target.h |   10 ++++++++++
 2 files changed, 46 insertions(+), 0 deletions(-)

diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index a2f85ff..767b347 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -318,6 +318,11 @@ static int tcg_target_const_match (tcg_target_long val,
 #define EXTSB  XO31(954)
 #define EXTSH  XO31(922)
 #define EXTSW  XO31(986)
+#define NAND   XO31(476)
+#define NOR    XO31(124)
+#define EQV    XO31(284)
+#define ANDC   XO31( 60)
+#define ORC    XO31(412)
 #define ADD    XO31(266)
 #define ADDE   XO31(138)
 #define ADDC   XO31( 10)
@@ -1189,6 +1194,27 @@ static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
             tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
         break;
 
+    case INDEX_op_andc_i32:
+    case INDEX_op_andc_i64:
+        tcg_out32 (s, ANDC | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_eqv_i32:
+    case INDEX_op_eqv_i64:
+        tcg_out32 (s, EQV | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_nand_i32:
+    case INDEX_op_nand_i64:
+        tcg_out32 (s, NAND | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_nor_i32:
+    case INDEX_op_nor_i64:
+        tcg_out32 (s, NOR | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_orc_i32:
+    case INDEX_op_orc_i64:
+        tcg_out32 (s, ORC | SAB (args[0], args[1], args[2]));
+        break;
+
     case INDEX_op_mul_i32:
         if (const_args[2]) {
             if (args[2] == (int16_t) args[2])
@@ -1424,6 +1450,11 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_and_i32, { "r", "r", "ri" } },
     { INDEX_op_or_i32, { "r", "r", "ri" } },
     { INDEX_op_xor_i32, { "r", "r", "ri" } },
+    { INDEX_op_andc_i32, { "r", "r", "r" } },
+    { INDEX_op_eqv_i32, { "r", "r", "r" } },
+    { INDEX_op_nand_i32, { "r", "r", "r" } },
+    { INDEX_op_nor_i32, { "r", "r", "r" } },
+    { INDEX_op_orc_i32, { "r", "r", "r" } },
 
     { INDEX_op_shl_i32, { "r", "r", "ri" } },
     { INDEX_op_shr_i32, { "r", "r", "ri" } },
@@ -1439,6 +1470,11 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_and_i64, { "r", "r", "rZ" } },
     { INDEX_op_or_i64, { "r", "r", "rZ" } },
     { INDEX_op_xor_i64, { "r", "r", "rZ" } },
+    { INDEX_op_andc_i64, { "r", "r", "r" } },
+    { INDEX_op_eqv_i64, { "r", "r", "r" } },
+    { INDEX_op_nand_i64, { "r", "r", "r" } },
+    { INDEX_op_nor_i64, { "r", "r", "r" } },
+    { INDEX_op_orc_i64, { "r", "r", "r" } },
 
     { INDEX_op_shl_i64, { "r", "r", "ri" } },
     { INDEX_op_shr_i64, { "r", "r", "ri" } },
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 452bfda..f0a4206 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -77,6 +77,16 @@ enum {
 #define TCG_TARGET_HAS_ext8s_i64
 #define TCG_TARGET_HAS_ext16s_i64
 #define TCG_TARGET_HAS_ext32s_i64
+#define TCG_TARGET_HAS_andc_i32
+#define TCG_TARGET_HAS_eqv_i32
+#define TCG_TARGET_HAS_nand_i32
+#define TCG_TARGET_HAS_nor_i32
+#define TCG_TARGET_HAS_orc_i32
+#define TCG_TARGET_HAS_andc_i64
+#define TCG_TARGET_HAS_eqv_i64
+#define TCG_TARGET_HAS_nand_i64
+#define TCG_TARGET_HAS_nor_i64
+#define TCG_TARGET_HAS_orc_i64
 
 #define TCG_AREG0 TCG_REG_R27
 #define TCG_AREG1 TCG_REG_R24
-- 
1.6.0.5