[Qemu-devel] [PATCH 0/9] tcg: improve logical op support for ppc hosts, v2

[Qemu-devel] [PATCH 0/9] tcg: improve logical op support for ppc hosts, v2

[Nathan Froyd]

This is version two of my patchset for improving codegen of logical ops
on ppc hosts, initially posted here:

http://lists.gnu.org/archive/html/qemu-devel/2009-03/msg01668.html

The changes from the first version are using TCG_TARGET_REG_BITS in the
implementation of 64-bit logical ops for 32-bit hosts and the removal of
the "remove r0 from the allocation pool" patch: a similar patch went in
earlier this month.

-Nathan

[Qemu-devel] [PATCH 1/9] Add TCG ops for various logical operations

[Nathan Froyd]

 andc, orc, nor, nand, and eqv, to be precise.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-opc.h |   32 ++++++++++++++++++++++++++++++++
 1 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 3a095fc..e4e1ce4 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -67,6 +67,22 @@ DEF2(divu2_i32, 2, 3, 0, 0)
 DEF2(and_i32, 1, 2, 0, 0)
 DEF2(or_i32, 1, 2, 0, 0)
 DEF2(xor_i32, 1, 2, 0, 0)
+#ifdef TCG_TARGET_HAS_andc_i32
+DEF2(andc_i32, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_eqv_i32
+DEF2(eqv_i32, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_nand_i32
+DEF2(nand_i32, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_nor_i32
+DEF2(nor_i32, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_orc_i32
+DEF2(orc_i32, 1, 2, 0, 0)
+#endif
+
 /* shifts/rotates */
 DEF2(shl_i32, 1, 2, 0, 0)
 DEF2(shr_i32, 1, 2, 0, 0)
@@ -133,6 +149,22 @@ DEF2(divu2_i64, 2, 3, 0, 0)
 DEF2(and_i64, 1, 2, 0, 0)
 DEF2(or_i64, 1, 2, 0, 0)
 DEF2(xor_i64, 1, 2, 0, 0)
+#ifdef TCG_TARGET_HAS_andc_i64
+DEF2(andc_i64, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_eqv_i64
+DEF2(eqv_i64, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_nand_i64
+DEF2(nand_i64, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_nor_i64
+DEF2(nor_i64, 1, 2, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_orc_i64
+DEF2(orc_i64, 1, 2, 0, 0)
+#endif
+
 /* shifts/rotates */
 DEF2(shl_i64, 1, 2, 0, 0)
 DEF2(shr_i64, 1, 2, 0, 0)
-- 
1.6.0.5

[Qemu-devel] [PATCH 2/9] specialize tcg_gen_not_i64 for 32-bit targets

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-op.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index daeb025..e56facd 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1515,6 +1515,9 @@ static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
 {
 #ifdef TCG_TARGET_HAS_not_i64
     tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
+#elif defined(TCG_TARGET_HAS_not_i32) && TCG_TARGET_REG_BITS == 32
+    tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
+    tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
 #else
     tcg_gen_xori_i64(ret, arg, -1);
 #endif
-- 
1.6.0.5

[Qemu-devel] [PATCH 3/9] implement specialized andc_i{32,64}

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-op.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index e56facd..d095077 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1573,20 +1573,31 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 hi
 
 static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_andc_i32
+    tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
+#else
     TCGv_i32 t0;
     t0 = tcg_temp_new_i32();
     tcg_gen_not_i32(t0, arg2);
     tcg_gen_and_i32(ret, arg1, t0);
     tcg_temp_free_i32(t0);
+#endif
 }
 
 static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_andc_i64
+    tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32
+    tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     TCGv_i64 t0;
     t0 = tcg_temp_new_i64();
     tcg_gen_not_i64(t0, arg2);
     tcg_gen_and_i64(ret, arg1, t0);
     tcg_temp_free_i64(t0);
+#endif
 }
 
 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-- 
1.6.0.5

[Qemu-devel] [PATCH 4/9] implement specialized eqv_{i32,i64}

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-op.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index d095077..543d1b6 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1602,14 +1602,25 @@ static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_eqv_i32
+    tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
+#else
     tcg_gen_xor_i32(ret, arg1, arg2);
     tcg_gen_not_i32(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_eqv_i64
+    tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_eqv_i32) && TCG_TARGET_REG_BITS == 32
+    tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     tcg_gen_xor_i64(ret, arg1, arg2);
     tcg_gen_not_i64(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-- 
1.6.0.5

[Qemu-devel] [PATCH 5/9] implement specialized nand_i{32,64}

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-op.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 543d1b6..13c0967 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1625,14 +1625,25 @@ static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_nand_i32
+    tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
+#else
     tcg_gen_and_i32(ret, arg1, arg2);
     tcg_gen_not_i32(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_nand_i64
+    tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_nand_i32) && TCG_TARGET_REG_BITS == 32
+    tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     tcg_gen_and_i64(ret, arg1, arg2);
     tcg_gen_not_i64(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-- 
1.6.0.5

[Qemu-devel] [PATCH 6/9] implement specialized nor_i{32,64}

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-op.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 13c0967..c763ac0 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1648,14 +1648,25 @@ static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_nor_i32
+    tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
+#else
     tcg_gen_or_i32(ret, arg1, arg2);
     tcg_gen_not_i32(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_nor_i64
+    tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_nor_i32) && TCG_TARGET_REG_BITS == 32
+    tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     tcg_gen_or_i64(ret, arg1, arg2);
     tcg_gen_not_i64(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-- 
1.6.0.5

[Qemu-devel] [PATCH 7/9] implement specialized orc_i{32,64}

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/tcg-op.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index c763ac0..31c88ba 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1671,20 +1671,31 @@ static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_orc_i32
+    tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
+#else
     TCGv_i32 t0;
     t0 = tcg_temp_new_i32();
     tcg_gen_not_i32(t0, arg2);
     tcg_gen_or_i32(ret, arg1, t0);
     tcg_temp_free_i32(t0);
+#endif
 }
 
 static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_orc_i64
+    tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32
+    tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     TCGv_i64 t0;
     t0 = tcg_temp_new_i64();
     tcg_gen_not_i64(t0, arg2);
     tcg_gen_or_i64(ret, arg1, t0);
     tcg_temp_free_i64(t0);
+#endif
 }
 
 static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
-- 
1.6.0.5

[Qemu-devel] [PATCH 8/9] Implement new logical instructions for ppc

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/ppc/tcg-target.c |   26 ++++++++++++++++++++++++++
 tcg/ppc/tcg-target.h |    5 +++++
 2 files changed, 31 insertions(+), 0 deletions(-)

diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index e3f4b59..4e83982 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -332,6 +332,11 @@ static int tcg_target_const_match(tcg_target_long val,
 
 #define EXTSB  XO31(954)
 #define EXTSH  XO31(922)
+#define NAND   XO31(476)
+#define NOR    XO31(124)
+#define EQV    XO31(284)
+#define ANDC   XO31( 60)
+#define ORC    XO31(412)
 #define ADD    XO31(266)
 #define ADDE   XO31(138)
 #define ADDC   XO31( 10)
@@ -1261,6 +1266,22 @@ static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
             tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
         break;
 
+    case INDEX_op_andc_i32:
+        tcg_out32 (s, ANDC | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_eqv_i32:
+        tcg_out32 (s, EQV | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_nand_i32:
+        tcg_out32 (s, NAND | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_nor_i32:
+        tcg_out32 (s, NOR | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_orc_i32:
+        tcg_out32 (s, ORC | SAB (args[0], args[1], args[2]));
+        break;
+
     case INDEX_op_mul_i32:
         if (const_args[2]) {
             if (args[2] == (int16_t) args[2])
@@ -1456,6 +1477,11 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_and_i32, { "r", "r", "ri" } },
     { INDEX_op_or_i32, { "r", "r", "ri" } },
     { INDEX_op_xor_i32, { "r", "r", "ri" } },
+    { INDEX_op_andc_i32, { "r", "r", "r" } },
+    { INDEX_op_eqv_i32, { "r", "r", "r" } },
+    { INDEX_op_nand_i32, { "r", "r", "r" } },
+    { INDEX_op_nor_i32, { "r", "r", "r" } },
+    { INDEX_op_orc_i32, { "r", "r", "r" } },
 
     { INDEX_op_shl_i32, { "r", "r", "ri" } },
     { INDEX_op_shr_i32, { "r", "r", "ri" } },
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 5faf730..385f0ff 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -81,6 +81,11 @@ enum {
 #define TCG_TARGET_HAS_div_i32
 #define TCG_TARGET_HAS_ext8s_i32
 #define TCG_TARGET_HAS_ext16s_i32
+#define TCG_TARGET_HAS_andc_i32
+#define TCG_TARGET_HAS_eqv_i32
+#define TCG_TARGET_HAS_nand_i32
+#define TCG_TARGET_HAS_nor_i32
+#define TCG_TARGET_HAS_orc_i32
 
 #define TCG_AREG0 TCG_REG_R27
 #define TCG_AREG1 TCG_REG_R24
-- 
1.6.0.5

[Qemu-devel] [PATCH 9/9] Implement new logical instructions for ppc64

[Nathan Froyd]

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 tcg/ppc64/tcg-target.c |   36 ++++++++++++++++++++++++++++++++++++
 tcg/ppc64/tcg-target.h |   10 ++++++++++
 2 files changed, 46 insertions(+), 0 deletions(-)

diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index a2f85ff..767b347 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -318,6 +318,11 @@ static int tcg_target_const_match (tcg_target_long val,
 #define EXTSB  XO31(954)
 #define EXTSH  XO31(922)
 #define EXTSW  XO31(986)
+#define NAND   XO31(476)
+#define NOR    XO31(124)
+#define EQV    XO31(284)
+#define ANDC   XO31( 60)
+#define ORC    XO31(412)
 #define ADD    XO31(266)
 #define ADDE   XO31(138)
 #define ADDC   XO31( 10)
@@ -1189,6 +1194,27 @@ static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
             tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
         break;
 
+    case INDEX_op_andc_i32:
+    case INDEX_op_andc_i64:
+        tcg_out32 (s, ANDC | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_eqv_i32:
+    case INDEX_op_eqv_i64:
+        tcg_out32 (s, EQV | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_nand_i32:
+    case INDEX_op_nand_i64:
+        tcg_out32 (s, NAND | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_nor_i32:
+    case INDEX_op_nor_i64:
+        tcg_out32 (s, NOR | SAB (args[0], args[1], args[2]));
+        break;
+    case INDEX_op_orc_i32:
+    case INDEX_op_orc_i64:
+        tcg_out32 (s, ORC | SAB (args[0], args[1], args[2]));
+        break;
+
     case INDEX_op_mul_i32:
         if (const_args[2]) {
             if (args[2] == (int16_t) args[2])
@@ -1424,6 +1450,11 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_and_i32, { "r", "r", "ri" } },
     { INDEX_op_or_i32, { "r", "r", "ri" } },
     { INDEX_op_xor_i32, { "r", "r", "ri" } },
+    { INDEX_op_andc_i32, { "r", "r", "r" } },
+    { INDEX_op_eqv_i32, { "r", "r", "r" } },
+    { INDEX_op_nand_i32, { "r", "r", "r" } },
+    { INDEX_op_nor_i32, { "r", "r", "r" } },
+    { INDEX_op_orc_i32, { "r", "r", "r" } },
 
     { INDEX_op_shl_i32, { "r", "r", "ri" } },
     { INDEX_op_shr_i32, { "r", "r", "ri" } },
@@ -1439,6 +1470,11 @@ static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_and_i64, { "r", "r", "rZ" } },
     { INDEX_op_or_i64, { "r", "r", "rZ" } },
     { INDEX_op_xor_i64, { "r", "r", "rZ" } },
+    { INDEX_op_andc_i64, { "r", "r", "r" } },
+    { INDEX_op_eqv_i64, { "r", "r", "r" } },
+    { INDEX_op_nand_i64, { "r", "r", "r" } },
+    { INDEX_op_nor_i64, { "r", "r", "r" } },
+    { INDEX_op_orc_i64, { "r", "r", "r" } },
 
     { INDEX_op_shl_i64, { "r", "r", "ri" } },
     { INDEX_op_shr_i64, { "r", "r", "ri" } },
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 452bfda..f0a4206 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -77,6 +77,16 @@ enum {
 #define TCG_TARGET_HAS_ext8s_i64
 #define TCG_TARGET_HAS_ext16s_i64
 #define TCG_TARGET_HAS_ext32s_i64
+#define TCG_TARGET_HAS_andc_i32
+#define TCG_TARGET_HAS_eqv_i32
+#define TCG_TARGET_HAS_nand_i32
+#define TCG_TARGET_HAS_nor_i32
+#define TCG_TARGET_HAS_orc_i32
+#define TCG_TARGET_HAS_andc_i64
+#define TCG_TARGET_HAS_eqv_i64
+#define TCG_TARGET_HAS_nand_i64
+#define TCG_TARGET_HAS_nor_i64
+#define TCG_TARGET_HAS_orc_i64
 
 #define TCG_AREG0 TCG_REG_R27
 #define TCG_AREG1 TCG_REG_R24
-- 
1.6.0.5

Re: [Qemu-devel] [PATCH 9/9] Implement new logical instructions for ppc64

[malc]

On Tue, 21 Apr 2009, Nathan Froyd wrote:

> 
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
>  tcg/ppc64/tcg-target.c |   36 ++++++++++++++++++++++++++++++++++++
>  tcg/ppc64/tcg-target.h |   10 ++++++++++
>  2 files changed, 46 insertions(+), 0 deletions(-)

[..snip..]

Have you measured the speed impact of this, if so how?

-- 
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Re: [Qemu-devel] [PATCH 9/9] Implement new logical instructions for ppc64

[Nathan Froyd]

On Wed, Apr 22, 2009 at 05:44:00PM +0400, malc wrote:
> On Tue, 21 Apr 2009, Nathan Froyd wrote:
> >  tcg/ppc64/tcg-target.c |   36 ++++++++++++++++++++++++++++++++++++
> >  tcg/ppc64/tcg-target.h |   10 ++++++++++
> >  2 files changed, 46 insertions(+), 0 deletions(-)
> 
> Have you measured the speed impact of this, if so how?

I have not.

-Nathan