From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M2Q9R-00023u-IF for qemu-devel@nongnu.org; Fri, 08 May 2009 09:30:10 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M2Q9L-00021h-9I for qemu-devel@nongnu.org; Fri, 08 May 2009 09:30:08 -0400 Received: from [199.232.76.173] (port=47025 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M2Q9J-00021X-Ab for qemu-devel@nongnu.org; Fri, 08 May 2009 09:30:02 -0400 Received: from mail.corp.accelance.fr ([213.162.48.15]:56837) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1M2Q9I-0002cP-Q4 for qemu-devel@nongnu.org; Fri, 08 May 2009 09:30:01 -0400 Received: from [192.168.0.5] (potipota.net [88.168.176.51]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.corp.accelance.fr (Postfix) with ESMTP id 7EB685A9912 for ; Fri, 8 May 2009 15:29:57 +0200 (CEST) From: Lionel Landwerlin Content-Type: text/plain Date: Fri, 08 May 2009 15:30:00 +0200 Message-Id: <1241789400.4188.2.camel@coalu.atr> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH] SH4: Added "TLB Invalidate Bit" management to MMUCR register List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org SH4: Added "TLB Invalidate Bit" management to MMUCR register Signed-off-by: Lionel Landwerlin --- hw/sh7750.c | 5 +++++ target-sh4/cpu.h | 2 ++ target-sh4/helper.c | 13 ++++++++++++- 3 files changed, 19 insertions(+), 1 deletions(-) diff --git a/hw/sh7750.c b/hw/sh7750.c index 423c43f..718ad53 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -397,6 +397,11 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, portb_changed(s, temp); return; case SH7750_MMUCR_A7: + if (s->cpu->mmucr & MMUCR_TLB_INVALIDATE) + { + cpu_sh4_tlbs_invalidate(s->cpu); + mem_value |= ~MMUCR_TLB_INVALIDATE; + } s->cpu->mmucr = mem_value; return; case SH7750_PTEH_A7: diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index e597f65..bf62e63 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -171,6 +171,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, uint32_t mem_value); int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr); +void cpu_sh4_tlbs_invalidate (CPUSH4State * env); static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls) { @@ -222,6 +223,7 @@ enum { /* MMU control register */ #define MMUCR 0x1F000010 #define MMUCR_AT (1<<0) +#define MMUCR_TLB_INVALIDATE (1<<2) #define MMUCR_SV (1<<8) #define MMUCR_URC_BITS (6) #define MMUCR_URC_OFFSET (10) diff --git a/target-sh4/helper.c b/target-sh4/helper.c index d8e08e3..979ec70 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -631,7 +631,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, if (needs_tlb_flush) tlb_flush_page(s, vpn << 10); - + } else { int index = (addr & 0x00003f00) >> 8; tlb_t * entry = &s->utlb[index]; @@ -694,4 +694,15 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) return 0; } +void cpu_sh4_tlbs_invalidate (CPUSH4State * env) +{ + int i; + + for (i = 0 ; i < ITLB_SIZE ; i++) + env->itlb[i].v = 0; + + for (i = 0 ; i < UTLB_SIZE ; i++) + env->utlb[i].v = 0; +} + #endif -- 1.6.2.4 -- Lionel Landwerlin