From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M3KeJ-0000X5-9j for qemu-devel@nongnu.org; Sun, 10 May 2009 21:49:47 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M3KeE-0000WZ-8Z for qemu-devel@nongnu.org; Sun, 10 May 2009 21:49:46 -0400 Received: from [199.232.76.173] (port=52603 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M3KeE-0000WV-0r for qemu-devel@nongnu.org; Sun, 10 May 2009 21:49:42 -0400 Received: from mga03.intel.com ([143.182.124.21]:33718) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1M3KeD-0006j9-Iv for qemu-devel@nongnu.org; Sun, 10 May 2009 21:49:41 -0400 From: Huang Ying In-Reply-To: <4A049F37.3040603@us.ibm.com> References: <1241419677.8815.42.camel@yhuang-dev.sh.intel.com> <4A049F37.3040603@us.ibm.com> Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-EcoJKCxzFAELctg29Qbz" Date: Mon, 11 May 2009 09:48:14 +0800 Message-Id: <1242006494.6259.163.camel@yhuang-dev.sh.intel.com> Mime-Version: 1.0 Subject: [Qemu-devel] Re: [RFC -v3 1/2] QEMU-KVM: MCE: Add MCE simulation to qemu/tcg List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: "kvm@vger.kernel.org" , Andi Kleen , Avi Kivity , "qemu-devel@nongnu.org" --=-EcoJKCxzFAELctg29Qbz Content-Type: text/plain Content-Transfer-Encoding: quoted-printable On Sat, 2009-05-09 at 05:08 +0800, Anthony Liguori wrote: > Huang Ying wrote: > > - MCE features are initialized when VCPU is intialized according to CPU= ID. > > - A monitor command "mce" is added to inject a MCE. > > - A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE. > > > > Signed-off-by: Huang Ying > > > > --- > > cpu-all.h | 4 ++ > > cpu-exec.c | 4 ++ > > monitor.c | 49 +++++++++++++++++++++++++++++++++ > > target-i386/cpu.h | 22 +++++++++++++++ > > target-i386/helper.c | 70 +++++++++++++++++++++++++++++++++++++++= +++++++++ > > target-i386/op_helper.c | 34 +++++++++++++++++++++++ > > 6 files changed, 183 insertions(+) > > > > --- a/target-i386/cpu.h > > +++ b/target-i386/cpu.h > > @@ -202,6 +202,7 @@ > > #define CR4_DE_MASK (1 << 3) > > #define CR4_PSE_MASK (1 << 4) > > #define CR4_PAE_MASK (1 << 5) > > +#define CR4_MCE_MASK (1 << 6) > > #define CR4_PGE_MASK (1 << 7) > > #define CR4_PCE_MASK (1 << 8) > > #define CR4_OSFXSR_SHIFT 9 > > @@ -248,6 +249,17 @@ > > #define PG_ERROR_RSVD_MASK 0x08 > > #define PG_ERROR_I_D_MASK 0x10 > > =20 > > +#define MCE_CAP_DEF 0x100 > > +#define MCE_BANKS_DEF 4 > > + > > +#define MCG_CTL_P (1UL<<8) > > + > > +#define MCG_STATUS_MCIP (1UL<<2) > > + > > +#define MCI_STATUS_VAL (1UL<<63) > > +#define MCI_STATUS_OVER (1UL<<62) > > +#define MCI_STATUS_UC (1UL<<61) > > + > > #define MSR_IA32_TSC 0x10 > > #define MSR_IA32_APICBASE 0x1b > > #define MSR_IA32_APICBASE_BSP (1<<8) > > @@ -288,6 +300,11 @@ > > =20 > > #define MSR_MTRRdefType 0x2ff > > =20 > > +#define MSR_MC0_CTL 0x400 > > +#define MSR_MC0_STATUS 0x401 > > +#define MSR_MC0_ADDR 0x402 > > +#define MSR_MC0_MISC 0x403 > > + > > #define MSR_EFER 0xc0000080 > > =20 > > #define MSR_EFER_SCE (1 << 0) > > @@ -674,6 +691,11 @@ typedef struct CPUX86State { > > user */ > > struct APICState *apic_state; > > uint32_t mp_state; > > + > > + uint64 mcg_cap; > > + uint64 mcg_status; > > + uint64 mcg_ctl; > > + uint64 *mce_banks; > > } CPUX86State; > > > > =20 >=20 > Doesn't this need to be added to the savevm/loadvm state? Yes. I will add it. Best Regards, Huang Ying --=-EcoJKCxzFAELctg29Qbz Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) iEYEABECAAYFAkoHg9sACgkQKhFGF+eHlpi+hwCfXxHaGf7iZJxkQeJ9CHC7jXwg 5xkAoJHbjb4K6y79277UH69fj9MR8xji =rM4H -----END PGP SIGNATURE----- --=-EcoJKCxzFAELctg29Qbz--