From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M40Xc-0006zp-7h for qemu-devel@nongnu.org; Tue, 12 May 2009 18:33:40 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M40XW-0006z2-Kd for qemu-devel@nongnu.org; Tue, 12 May 2009 18:33:38 -0400 Received: from [199.232.76.173] (port=57709 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M40XW-0006yz-JL for qemu-devel@nongnu.org; Tue, 12 May 2009 18:33:34 -0400 Received: from g5t0007.atlanta.hp.com ([15.192.0.44]:2050) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1M40XW-000334-45 for qemu-devel@nongnu.org; Tue, 12 May 2009 18:33:34 -0400 From: Alex Williamson Content-Type: text/plain Date: Tue, 12 May 2009 16:33:10 -0600 Message-Id: <1242167590.4788.20.camel@2710p.home> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH] bios: Use the correct mask to size the PCI option ROM BAR List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel Cc: kvm-devel Bit 0 is the enable bit, which we not only don't want to set, but it will stick and make us think it's an I/O port resource. Signed-off-by: Alex Williamson --- diff --git a/bios/rombios32.c b/bios/rombios32.c index d7e18e9..f861f81 100644 --- a/bios/rombios32.c +++ b/bios/rombios32.c @@ -985,11 +985,13 @@ static void pci_bios_init_device(PCIDevice *d) int ofs; uint32_t val, size ; - if (i == PCI_ROM_SLOT) + if (i == PCI_ROM_SLOT) { ofs = 0x30; - else + pci_config_writel(d, ofs, 0xfffffffe); + } else { ofs = 0x10 + i * 4; - pci_config_writel(d, ofs, 0xffffffff); + pci_config_writel(d, ofs, 0xffffffff); + } val = pci_config_readl(d, ofs); if (val != 0) { size = (~(val & ~0xf)) + 1;