[Qemu-devel] [PATCH] bios: Use the correct mask to size the PCI option ROM BAR

[Qemu-devel] [PATCH] bios: Use the correct mask to size the PCI option ROM BAR

[Alex Williamson]

Bit 0 is the enable bit, which we not only don't want to set, but
it will stick and make us think it's an I/O port resource.

Signed-off-by: Alex Williamson <alex.williamson@hp.com>
---

diff --git a/bios/rombios32.c b/bios/rombios32.c
index d7e18e9..f861f81 100644
--- a/bios/rombios32.c
+++ b/bios/rombios32.c
@@ -985,11 +985,13 @@ static void pci_bios_init_device(PCIDevice *d)
             int ofs;
             uint32_t val, size ;
 
-            if (i == PCI_ROM_SLOT)
+            if (i == PCI_ROM_SLOT) {
                 ofs = 0x30;
-            else
+                pci_config_writel(d, ofs, 0xfffffffe);
+            } else {
                 ofs = 0x10 + i * 4;
-            pci_config_writel(d, ofs, 0xffffffff);
+                pci_config_writel(d, ofs, 0xffffffff);
+            }
             val = pci_config_readl(d, ofs);
             if (val != 0) {
                 size = (~(val & ~0xf)) + 1;

Re: [Qemu-devel] [PATCH] bios: Use the correct mask to size the PCI option ROM BAR

[Paul Brook]

On Tuesday 12 May 2009, Alex Williamson wrote:
> Bit 0 is the enable bit, which we not only don't want to set, but
> it will stick and make us think it's an I/O port resource.

Why is the ROM slot special? Doesn't the same apply to all BARs?

Paul

Re: [Qemu-devel] [PATCH] bios: Use the correct mask to size the PCI option ROM BAR

[Alex Williamson]

On Tue, 2009-05-12 at 23:41 +0100, Paul Brook wrote:
> On Tuesday 12 May 2009, Alex Williamson wrote:
> > Bit 0 is the enable bit, which we not only don't want to set, but
> > it will stick and make us think it's an I/O port resource.
> 
> Why is the ROM slot special? Doesn't the same apply to all BARs?

The PCI option (or expansion) ROM is assumed to be in MMIO space, so bit
0 becomes the enable bit rather than the memory space flag.  The option
ROM is also only a 4 byte register.  The regular 6 base address
registers can support MMIO or I/O port addresses and for PCI 2.0 (iirc),
2 regular base address registers can be combined to describe an 8 byte
address.  You can look at drivers/pci/probe.c:__pci_read_base() in the
Linux source code and note that it makes the same special case for
sizing the ROM BAR (~PCI_ROM_ADDRESS_ENABLE vs ~0).

Alex