From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M41hC-0004k8-Gp for qemu-devel@nongnu.org; Tue, 12 May 2009 19:47:38 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M41h7-0004jw-TP for qemu-devel@nongnu.org; Tue, 12 May 2009 19:47:37 -0400 Received: from [199.232.76.173] (port=51931 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M41h7-0004jt-LE for qemu-devel@nongnu.org; Tue, 12 May 2009 19:47:33 -0400 Received: from mx20.gnu.org ([199.232.41.8]:56806) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1M41h7-0007gR-4M for qemu-devel@nongnu.org; Tue, 12 May 2009 19:47:33 -0400 Received: from g4t0015.houston.hp.com ([15.201.24.18]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1M41h6-0005jC-78 for qemu-devel@nongnu.org; Tue, 12 May 2009 19:47:32 -0400 Subject: Re: [Qemu-devel] [PATCH] bios: Use the correct mask to size the PCI option ROM BAR From: Alex Williamson In-Reply-To: <200905122341.40706.paul@codesourcery.com> References: <1242167590.4788.20.camel@2710p.home> <200905122341.40706.paul@codesourcery.com> Content-Type: text/plain Date: Tue, 12 May 2009 17:47:22 -0600 Message-Id: <1242172042.4788.42.camel@2710p.home> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paul Brook Cc: qemu-devel@nongnu.org, kvm-devel On Tue, 2009-05-12 at 23:41 +0100, Paul Brook wrote: > On Tuesday 12 May 2009, Alex Williamson wrote: > > Bit 0 is the enable bit, which we not only don't want to set, but > > it will stick and make us think it's an I/O port resource. > > Why is the ROM slot special? Doesn't the same apply to all BARs? The PCI option (or expansion) ROM is assumed to be in MMIO space, so bit 0 becomes the enable bit rather than the memory space flag. The option ROM is also only a 4 byte register. The regular 6 base address registers can support MMIO or I/O port addresses and for PCI 2.0 (iirc), 2 regular base address registers can be combined to describe an 8 byte address. You can look at drivers/pci/probe.c:__pci_read_base() in the Linux source code and note that it makes the same special case for sizing the ROM BAR (~PCI_ROM_ADDRESS_ENABLE vs ~0). Alex