From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M6sqb-0004ov-C2 for qemu-devel@nongnu.org; Wed, 20 May 2009 16:57:09 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M6sqV-0004lV-5o for qemu-devel@nongnu.org; Wed, 20 May 2009 16:57:07 -0400 Received: from [199.232.76.173] (port=43646 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M6sqU-0004lP-89 for qemu-devel@nongnu.org; Wed, 20 May 2009 16:57:02 -0400 Received: from mail-fx0-f219.google.com ([209.85.220.219]:44012) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1M6sqT-0003BC-PS for qemu-devel@nongnu.org; Wed, 20 May 2009 16:57:01 -0400 Received: by mail-fx0-f219.google.com with SMTP id 19so631463fxm.34 for ; Wed, 20 May 2009 13:57:01 -0700 (PDT) From: "Edgar E. Iglesias" Date: Wed, 20 May 2009 22:56:08 +0200 Message-Id: <1242852975-31043-6-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1242852975-31043-5-git-send-email-edgar.iglesias@gmail.com> References: <1242852975-31043-1-git-send-email-edgar.iglesias@gmail.com> <1242852975-31043-2-git-send-email-edgar.iglesias@gmail.com> <1242852975-31043-3-git-send-email-edgar.iglesias@gmail.com> <1242852975-31043-4-git-send-email-edgar.iglesias@gmail.com> <1242852975-31043-5-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH 06/13] microblaze: Add CPU interrupt wrapper logic. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- hw/microblaze_pic_cpu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 50 insertions(+), 0 deletions(-) create mode 100644 hw/microblaze_pic_cpu.c diff --git a/hw/microblaze_pic_cpu.c b/hw/microblaze_pic_cpu.c new file mode 100644 index 0000000..7c59382 --- /dev/null +++ b/hw/microblaze_pic_cpu.c @@ -0,0 +1,50 @@ +/* + * QEMU MicroBlaze CPU interrupt wrapper logic. + * + * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hw.h" +#include "pc.h" + +#define D(x) + +void pic_info(Monitor *mon) +{} +void irq_info(Monitor *mon) +{} + +static void microblaze_pic_cpu_handler(void *opaque, int irq, int level) +{ + CPUState *env = (CPUState *)opaque; + int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; + + if (level) + cpu_interrupt(env, type); + else + cpu_reset_interrupt(env, type); +} + +qemu_irq *microblaze_pic_init_cpu(CPUState *env); +qemu_irq *microblaze_pic_init_cpu(CPUState *env) +{ + return qemu_allocate_irqs(microblaze_pic_cpu_handler, env, 2); +} -- 1.6.0.6