[Qemu-devel] [PATCH 12/16] Peripheral driver for S3C SOC NAND controller

[Vincent Sanders <vince@simtec.co.uk>]

Signed-off-by: Vincent Sanders <vince@simtec.co.uk>
---
 Makefile.target   |    2 +-
 hw/s3c2410x.c     |    6 ++
 hw/s3c2440.c      |    6 ++
 hw/s3c24xx.h      |   10 ++++
 hw/s3c24xx_nand.c |  147 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 170 insertions(+), 1 deletions(-)
 create mode 100644 hw/s3c24xx_nand.c

diff --git a/Makefile.target b/Makefile.target
index 0d33486..535b4a2 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -650,7 +650,7 @@ OBJS+= mst_fpga.o mainstone.o
 OBJS+= musicpal.o pflash_cfi02.o
 OBJS+= s3c24xx_memc.o s3c24xx_irq.o s3c24xx_clkcon.o s3c24xx_timers.o
 OBJS+= s3c24xx_serial.o s3c24xx_rtc.o s3c24xx_gpio.o s3c24xx_iic.o
-OBJS+= s3c24xx_lcd.o
+OBJS+= s3c24xx_lcd.o s3c24xx_nand.o
 OBJS+= s3c2410x.o s3c2440.o
 OBJS+= framebuffer.o
 OBJS+= syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
diff --git a/hw/s3c2410x.c b/hw/s3c2410x.c
index 42cd2a8..78b9ee0 100644
--- a/hw/s3c2410x.c
+++ b/hw/s3c2410x.c
@@ -35,6 +35,9 @@
 /* LCD controller */
 #define CPU_S3C2410X_LCD_BASE (CPU_S3C2410X_PERIPHERAL + 0xD000000)
 
+/* NAND */
+#define CPU_S3C2410X_NAND_BASE (CPU_S3C2410X_PERIPHERAL + 0xE000000)
+
 /* serial port bases */
 #define CPU_S3C2410X_SERIAL0_BASE (CPU_S3C2410X_PERIPHERAL + 0x10000000)
 #define CPU_S3C2410X_SERIAL1_BASE (CPU_S3C2410X_PERIPHERAL + 0x10004000)
@@ -104,5 +107,8 @@ s3c2410x_init(int sdram_size)
     s->lcd = s3c24xx_lcd_init(CPU_S3C2410X_LCD_BASE,
                               s3c24xx_get_irq(s->irq, 16));
 
+    /* NAND controller */
+    s->nand = s3c24xx_nand_init(CPU_S3C2410X_NAND_BASE);
+
     return s;
 }
diff --git a/hw/s3c2440.c b/hw/s3c2440.c
index 3d32c03..fdb107b 100644
--- a/hw/s3c2440.c
+++ b/hw/s3c2440.c
@@ -34,6 +34,9 @@
 /* LCD controller */
 #define CPU_S3C2440_LCD_BASE (CPU_S3C2440_PERIPHERAL + 0xD000000)
 
+/* NAND */
+#define CPU_S3C2440_NAND_BASE (CPU_S3C2440_PERIPHERAL + 0xE000000)
+
 /* serial port bases */
 #define CPU_S3C2440_SERIAL0_BASE (CPU_S3C2440_PERIPHERAL + 0x10000000)
 #define CPU_S3C2440_SERIAL1_BASE (CPU_S3C2440_PERIPHERAL + 0x10004000)
@@ -101,5 +104,8 @@ s3c2440_init(int sdram_size)
     s->lcd = s3c24xx_lcd_init(CPU_S3C2440_LCD_BASE,
                               s3c24xx_get_irq(s->irq, 16));
 
+    /* NAND controller */
+    s->nand = s3c24xx_nand_init(CPU_S3C2440_NAND_BASE);
+
     return s;
 }
diff --git a/hw/s3c24xx.h b/hw/s3c24xx.h
index 2fdc3e8..af73ce5 100644
--- a/hw/s3c24xx.h
+++ b/hw/s3c24xx.h
@@ -11,6 +11,8 @@
 #ifndef S3C24XX_H
 #define S3C24XX_H 1
 
+#include "flash.h"
+
 /* This structure type encapsulates the state of a S3C24XX SoC. */
 typedef struct S3CState_s {
     CPUState *cpu_env;
@@ -42,6 +44,8 @@ typedef struct S3CState_s {
     /* LCD controller state */
     struct s3c24xx_lcd_state_s *lcd;
 
+    /* NAND controller */
+    struct s3c24xx_nand_state_s *nand;
 } S3CState;
 
 
@@ -81,4 +85,10 @@ i2c_bus *s3c24xx_i2c_bus(struct s3c24xx_i2c_state_s *s);
 /* Initialise LCD controller */
 struct s3c24xx_lcd_state_s *s3c24xx_lcd_init(target_phys_addr_t base, qemu_irq irq);
 
+/* Initialise nand controller */
+struct s3c24xx_nand_state_s *s3c24xx_nand_init(target_phys_addr_t base_addr);
+
+/* set nand controller context */
+void s3c24xx_nand_attach(struct s3c24xx_nand_state_s *s, NANDFlashState *nand);
+
 #endif /* S3C24XX_H */
diff --git a/hw/s3c24xx_nand.c b/hw/s3c24xx_nand.c
new file mode 100644
index 0000000..3c1ffa4
--- /dev/null
+++ b/hw/s3c24xx_nand.c
@@ -0,0 +1,147 @@
+/* hw/s3c24xx_nand.c
+ *
+ * Samsung S3C24XX NAND emulation
+ *
+ * Copyright 2006, 2008 Ben Dooks, Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+
+#include "s3c24xx.h"
+
+#define NFCONF 0
+#define NFCMD 1
+#define NFADDR 2
+#define NFDATA 3
+#define NFSTAT 4
+#define NFECC 5
+
+#define NFCE ((s->nand_reg[NFCONF] & 1<<11) != 0)
+
+/* NAND controller state */
+struct s3c24xx_nand_state_s {
+    uint32_t nand_reg[13];
+
+    NANDFlashState *nand;
+};
+
+static void
+s3c24xx_nand_write_f(void *opaque, target_phys_addr_t addr,
+                     uint32_t value)
+{
+    struct s3c24xx_nand_state_s *s = (struct s3c24xx_nand_state_s *)opaque;
+    int reg = (addr & 0x1f) >> 2;
+
+    if ((reg != NFCONF) && ((s->nand_reg[NFCONF] & 1<<15) == 0)) {
+        return; /* Ignore the write, the nand is not enabled */
+    }
+
+    switch (reg) {
+    case NFCONF:
+        s->nand_reg[reg] = value;
+        if (s->nand != NULL)
+            nand_setpins(s->nand, 0, 0, NFCE, 1, 0);
+        break;
+
+    case NFCMD:
+        s->nand_reg[reg] = value;
+        if (s->nand != NULL) {
+            nand_setpins(s->nand, 1, 0, NFCE, 1, 0);
+            nand_setio(s->nand, value);
+        }
+        break;
+
+    case NFADDR:
+        s->nand_reg[reg] = value;
+        if (s->nand != NULL) {
+            nand_setpins(s->nand, 0, 1, NFCE, 1, 0);
+            nand_setio(s->nand, value);
+        }
+        break;
+
+    case NFDATA:
+        s->nand_reg[reg] = value;
+        if (s->nand != NULL) {
+            nand_setpins(s->nand, 0, 0, NFCE, 1, 0);
+            nand_setio(s->nand, value);
+        }
+        break;
+
+    default:
+        /* Do nothing because the other registers are read only */
+        break;
+    }
+}
+
+static uint32_t
+s3c24xx_nand_read_f(void *opaque, target_phys_addr_t addr)
+{
+    struct s3c24xx_nand_state_s *s = (struct s3c24xx_nand_state_s *)opaque;
+    int reg = (addr & 0x1f) >> 2;
+    uint32_t ret = s->nand_reg[reg];
+
+    switch (reg) {
+    case NFDATA:
+        if (s->nand != NULL) {
+            nand_setpins(s->nand, 0, 0, NFCE, 1, 0);
+            ret = s->nand_reg[reg] = nand_getio(s->nand);
+        } else {
+            ret = s->nand_reg[ret] = 0;
+        }
+        break;
+
+    case NFSTAT:
+        if (s->nand != NULL) {
+            nand_getpins(s->nand, (int *)&ret);
+            s->nand_reg[reg] = ret;
+        } else {
+            ret = s->nand_reg[ret] = 0;
+        }
+
+    default:
+        /* The rest read-back what was written to them */
+        break;
+    }
+
+    return ret;
+}
+
+static CPUReadMemoryFunc *s3c24xx_nand_read[] = {
+    &s3c24xx_nand_read_f,
+    &s3c24xx_nand_read_f,
+    &s3c24xx_nand_read_f,
+};
+
+static CPUWriteMemoryFunc *s3c24xx_nand_write[] = {
+    &s3c24xx_nand_write_f,
+    &s3c24xx_nand_write_f,
+    &s3c24xx_nand_write_f,
+};
+
+struct s3c24xx_nand_state_s *
+s3c24xx_nand_init(target_phys_addr_t base_addr)
+{
+    struct s3c24xx_nand_state_s *s;
+    int tag;
+
+    s = qemu_mallocz(sizeof(struct s3c24xx_nand_state_s));
+
+    tag = cpu_register_io_memory(0, s3c24xx_nand_read, s3c24xx_nand_write, s);
+    cpu_register_physical_memory(base_addr, 0x40, tag);
+
+    return s;
+}
+
+void
+s3c24xx_nand_attach(struct s3c24xx_nand_state_s *s, NANDFlashState *nand)
+{
+    if (s->nand != NULL) {
+        /* Detach current nand device */
+        /* no cmd, no addr, not enabled, write protected, no 'gnd' */
+        nand_setpins(s->nand, 0, 0, 1, 0, 0);
+    }
+    s->nand = nand;
+}
-- 
1.6.0.4