[Qemu-devel] [PATCH 02/16] S3C2410 and S3C2440 core SOC implementation.

[Vincent Sanders <vince@simtec.co.uk>]

Signed-off-by: Vincent Sanders <vince@simtec.co.uk>
---
 Makefile.target |    1 +
 hw/s3c2410x.c   |   41 +++++++++++++++++++++++++++++++++++++++++
 hw/s3c2410x.h   |   38 ++++++++++++++++++++++++++++++++++++++
 hw/s3c2440.c    |   40 ++++++++++++++++++++++++++++++++++++++++
 hw/s3c2440.h    |   38 ++++++++++++++++++++++++++++++++++++++
 hw/s3c24xx.h    |   19 +++++++++++++++++++
 6 files changed, 177 insertions(+), 0 deletions(-)
 create mode 100644 hw/s3c2410x.c
 create mode 100644 hw/s3c2410x.h
 create mode 100644 hw/s3c2440.c
 create mode 100644 hw/s3c2440.h
 create mode 100644 hw/s3c24xx.h

diff --git a/Makefile.target b/Makefile.target
index 664a1e3..2e4c0f2 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -648,6 +648,7 @@ OBJS+= omap_sx1.o palm.o tsc210x.o
 OBJS+= nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o
 OBJS+= mst_fpga.o mainstone.o
 OBJS+= musicpal.o pflash_cfi02.o
+OBJS+= s3c2410x.o s3c2440.o
 OBJS+= framebuffer.o
 OBJS+= syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
 OBJS+= syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o
diff --git a/hw/s3c2410x.c b/hw/s3c2410x.c
new file mode 100644
index 0000000..0461095
--- /dev/null
+++ b/hw/s3c2410x.c
@@ -0,0 +1,41 @@
+/* hw/s3c2410x.c
+ *
+ * Samsung S3C2410X emulation
+ *
+ * Copyright 2009 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+
+#include "s3c2410x.h"
+
+/* Integrated peripherals */
+#define CPU_S3C2410X_SRAM_BASE (CPU_S3C2410X_PERIPHERAL + 0x00000000)
+#define CPU_S3C2410X_SRAM_SIZE 4096
+
+/* Initialise a Samsung S3C2410X SOC ARM core and internal peripherals. */
+S3CState *
+s3c2410x_init(int sdram_size)
+{
+    S3CState *s = (S3CState *)qemu_mallocz(sizeof(S3CState));
+
+    /* Prepare the ARM 920T core */
+    s->cpu_env = cpu_init("arm920t");
+
+    /* S3C2410X SDRAM memory is always at the same physical location */
+    cpu_register_physical_memory(CPU_S3C2410X_DRAM,
+                                 ram_size,
+                                 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
+
+
+    /* S3C2410X SRAM */
+    cpu_register_physical_memory(CPU_S3C2410X_SRAM_BASE,
+                                 CPU_S3C2410X_SRAM_SIZE,
+                                 qemu_ram_alloc(CPU_S3C2410X_SRAM_SIZE) | IO_MEM_RAM);
+
+
+    return s;
+}
diff --git a/hw/s3c2410x.h b/hw/s3c2410x.h
new file mode 100644
index 0000000..f21bf9c
--- /dev/null
+++ b/hw/s3c2410x.h
@@ -0,0 +1,38 @@
+/* hw/s3c2410x.h
+ *
+ * Samsung s3c2410x cpu register definitions
+ *
+ * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2.
+ */
+
+#ifndef S3C2410X_H
+#define S3C2410X_H 1
+
+#include "s3c24xx.h"
+
+/* S3C2410 Physical memory areas */
+
+/* Chip select 0, Read only, not wired for write */
+#define CPU_S3C2410X_CS0 (0x00000000)
+/* Chip select 1 */
+#define CPU_S3C2410X_CS1 (0x08000000)
+/* Chip select 2 */
+#define CPU_S3C2410X_CS2 (0x10000000)
+/* Chip select 3 */
+#define CPU_S3C2410X_CS3 (0x18000000)
+/* Chip select 4 */
+#define CPU_S3C2410X_CS4 (0x20000000)
+/* Chip select 5 */
+#define CPU_S3C2410X_CS5 (0x28000000)
+/* Dynamic RAM */
+#define CPU_S3C2410X_DRAM (0x30000000)
+/* SOC Internal peripherals */
+#define CPU_S3C2410X_PERIPHERAL (0x40000000)
+
+/* s3c2410 SOC initialisation */
+S3CState *s3c2410x_init(int sdram_size);
+
+#endif /* S3C2410X_H */
diff --git a/hw/s3c2440.c b/hw/s3c2440.c
new file mode 100644
index 0000000..0d01ac6
--- /dev/null
+++ b/hw/s3c2440.c
@@ -0,0 +1,40 @@
+/* hw/s3c2440.c
+ *
+ * Samsung S3C2440 emulation
+ *
+ * Copyright 2009 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+
+#include "s3c2440.h"
+
+/* Integrated peripherals */
+#define CPU_S3C2440_SRAM_BASE (CPU_S3C2440_PERIPHERAL + 0x00000000)
+#define CPU_S3C2440_SRAM_SIZE 4096
+
+
+/* Initialise a Samsung S3C2440 SOC ARM core and internal peripherals. */
+S3CState *
+s3c2440_init(int sdram_size)
+{
+    S3CState *s = (S3CState *)qemu_mallocz(sizeof(S3CState));
+
+    /* Prepare the ARM 920T core */
+    s->cpu_env = cpu_init("arm920t");
+
+    /* S3C2440X SDRAM memory is always at the same physical location */
+    cpu_register_physical_memory(CPU_S3C2440_DRAM,
+                                 ram_size,
+                                 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
+
+    /* S3C2440 SRAM */
+    cpu_register_physical_memory(CPU_S3C2440_SRAM_BASE,
+                                 CPU_S3C2440_SRAM_SIZE,
+                                 qemu_ram_alloc(CPU_S3C2440_SRAM_SIZE) | IO_MEM_RAM);
+
+    return s;
+}
diff --git a/hw/s3c2440.h b/hw/s3c2440.h
new file mode 100644
index 0000000..d60ba44
--- /dev/null
+++ b/hw/s3c2440.h
@@ -0,0 +1,38 @@
+/* hw/s3c2410x.h
+ *
+ * Samsung s3c2410x cpu register definitions
+ *
+ * Copyright 2009 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2.
+ */
+
+#ifndef S3C2440_H
+#define S3C2440_H 1
+
+#include "s3c24xx.h"
+
+/* S3C2440 Physical memory areas */
+
+/* Chip select 0 */
+#define CPU_S3C2440_CS0 (0x00000000)
+/* Chip select 1 */
+#define CPU_S3C2440_CS1 (0x08000000)
+/* Chip select 2 */
+#define CPU_S3C2440_CS2 (0x10000000)
+/* Chip select 3 */
+#define CPU_S3C2440_CS3 (0x18000000)
+/* Chip select 4 */
+#define CPU_S3C2440_CS4 (0x20000000)
+/* Chip select 5 */
+#define CPU_S3C2440_CS5 (0x28000000)
+/* Dynamic RAM */
+#define CPU_S3C2440_DRAM (0x30000000)
+/* SOC Integrated peripherals */
+#define CPU_S3C2440_PERIPHERAL (0x40000000)
+
+/* s3c2440 SOC initialisation */
+S3CState *s3c2440_init(int sdram_size);
+
+#endif /* S3C2440_H */
diff --git a/hw/s3c24xx.h b/hw/s3c24xx.h
new file mode 100644
index 0000000..0b933c9
--- /dev/null
+++ b/hw/s3c24xx.h
@@ -0,0 +1,19 @@
+/* hw/s3c24xx.h
+ *
+ * Samsung s3c24xx cpu state and functions.
+ *
+ * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2.
+ */
+
+#ifndef S3C24XX_H
+#define S3C24XX_H 1
+
+/* This structure type encapsulates the state of a S3C24XX SoC. */
+typedef struct S3CState_s {
+    CPUState *cpu_env;
+} S3CState;
+
+#endif /* S3C24XX_H */
-- 
1.6.0.4