[Qemu-devel] [PATCH 03/16] Peripheral driver for S3C SOC SDRAM controller.

[Vincent Sanders <vince@simtec.co.uk>]

Peripheral driver for SDRAM controller on s3c24xx SOC. Very similar to
the implementation of other such controllers in that it just backs the
registers.

Signed-off-by: Vincent Sanders <vince@simtec.co.uk>
---
 Makefile.target   |    1 +
 hw/s3c2410x.c     |    9 +++++
 hw/s3c2440.c      |    8 ++++
 hw/s3c24xx.h      |    8 ++++
 hw/s3c24xx_memc.c |   96 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 122 insertions(+), 0 deletions(-)
 create mode 100644 hw/s3c24xx_memc.c

diff --git a/Makefile.target b/Makefile.target
index 2e4c0f2..2ecfeca 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -648,6 +648,7 @@ OBJS+= omap_sx1.o palm.o tsc210x.o
 OBJS+= nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o
 OBJS+= mst_fpga.o mainstone.o
 OBJS+= musicpal.o pflash_cfi02.o
+OBJS+= s3c24xx_memc.o
 OBJS+= s3c2410x.o s3c2440.o
 OBJS+= framebuffer.o
 OBJS+= syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
diff --git a/hw/s3c2410x.c b/hw/s3c2410x.c
index 0461095..74c61ac 100644
--- a/hw/s3c2410x.c
+++ b/hw/s3c2410x.c
@@ -13,9 +13,15 @@
 #include "s3c2410x.h"
 
 /* Integrated peripherals */
+
+/* SRAM */
 #define CPU_S3C2410X_SRAM_BASE (CPU_S3C2410X_PERIPHERAL + 0x00000000)
 #define CPU_S3C2410X_SRAM_SIZE 4096
 
+/* Memory control */
+#define CPU_S3C2410X_MEMC_BASE (CPU_S3C2410X_PERIPHERAL + 0x8000000)
+
+
 /* Initialise a Samsung S3C2410X SOC ARM core and internal peripherals. */
 S3CState *
 s3c2410x_init(int sdram_size)
@@ -37,5 +43,8 @@ s3c2410x_init(int sdram_size)
                                  qemu_ram_alloc(CPU_S3C2410X_SRAM_SIZE) | IO_MEM_RAM);
 
 
+    /* SDRAM memory controller */
+    s->memc = s3c24xx_memc_init(CPU_S3C2410X_MEMC_BASE);
+
     return s;
 }
diff --git a/hw/s3c2440.c b/hw/s3c2440.c
index 0d01ac6..18d8715 100644
--- a/hw/s3c2440.c
+++ b/hw/s3c2440.c
@@ -13,9 +13,14 @@
 #include "s3c2440.h"
 
 /* Integrated peripherals */
+
+/* SRAM */
 #define CPU_S3C2440_SRAM_BASE (CPU_S3C2440_PERIPHERAL + 0x00000000)
 #define CPU_S3C2440_SRAM_SIZE 4096
 
+/* Memory control */
+#define CPU_S3C2440_MEMC_BASE (CPU_S3C2440_PERIPHERAL + 0x8000000)
+
 
 /* Initialise a Samsung S3C2440 SOC ARM core and internal peripherals. */
 S3CState *
@@ -36,5 +41,8 @@ s3c2440_init(int sdram_size)
                                  CPU_S3C2440_SRAM_SIZE,
                                  qemu_ram_alloc(CPU_S3C2440_SRAM_SIZE) | IO_MEM_RAM);
 
+    /* SDRAM memory controller */
+    s->memc = s3c24xx_memc_init(CPU_S3C2440_MEMC_BASE);
+
     return s;
 }
diff --git a/hw/s3c24xx.h b/hw/s3c24xx.h
index 0b933c9..475bb2e 100644
--- a/hw/s3c24xx.h
+++ b/hw/s3c24xx.h
@@ -14,6 +14,14 @@
 /* This structure type encapsulates the state of a S3C24XX SoC. */
 typedef struct S3CState_s {
     CPUState *cpu_env;
+
+    /* Memory controller state */
+    struct s3c24xx_memc_state_s *memc;
+
 } S3CState;
 
+
+/* initialise memory controller peripheral */
+struct s3c24xx_memc_state_s *s3c24xx_memc_init(target_phys_addr_t base_addr);
+
 #endif /* S3C24XX_H */
diff --git a/hw/s3c24xx_memc.c b/hw/s3c24xx_memc.c
new file mode 100644
index 0000000..26964ca
--- /dev/null
+++ b/hw/s3c24xx_memc.c
@@ -0,0 +1,96 @@
+/* hw/s3c24xx_memc.c
+ *
+ * Samsung S3C24XX memory controller emulation.
+ *
+ * The SDRAM controller on several S3C SOC is generic, the emulation needs to
+ * be little more than backing the registers.
+ *
+ * Copyright 2006, 2007 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+
+#include "s3c24xx.h"
+
+/* Memory controller state */
+struct s3c24xx_memc_state_s {
+    uint32_t memc_reg[13];
+};
+
+static void
+s3c24xx_memc_write_f(void *opaque, target_phys_addr_t addr_, uint32_t value)
+{
+    struct s3c24xx_memc_state_s *s = (struct s3c24xx_memc_state_s *)opaque;
+    int addr = (addr_ & 0x3f) >> 2;
+
+    if (addr < 0 || addr > 12)
+        addr = 12;
+
+    s->memc_reg[addr] = value;
+}
+
+static uint32_t
+s3c24xx_memc_read_f(void *opaque, target_phys_addr_t addr_)
+{
+    struct s3c24xx_memc_state_s *s = (struct s3c24xx_memc_state_s *)opaque;
+    int addr = (addr_ & 0x3f) >> 2;
+
+    if (addr < 0 || addr > 12)
+        addr = 12;
+
+    return s->memc_reg[addr];
+}
+
+static CPUReadMemoryFunc *s3c24xx_memc_read[] = {
+    &s3c24xx_memc_read_f,
+    &s3c24xx_memc_read_f,
+    &s3c24xx_memc_read_f,
+};
+
+static CPUWriteMemoryFunc *s3c24xx_memc_write[] = {
+    &s3c24xx_memc_write_f,
+    &s3c24xx_memc_write_f,
+    &s3c24xx_memc_write_f,
+};
+
+static void s3c24xx_memc_save(QEMUFile *f, void *opaque)
+{
+    struct s3c24xx_memc_state_s *s = (struct s3c24xx_memc_state_s *)opaque;
+    int i;
+
+    for (i = 0; i < 13; i ++)
+        qemu_put_be32s(f, &s->memc_reg[i]);
+}
+
+static int s3c24xx_memc_load(QEMUFile *f, void *opaque, int version_id)
+{
+    struct s3c24xx_memc_state_s *s = (struct s3c24xx_memc_state_s *)opaque;
+    int i;
+
+    for (i = 0; i < 13; i ++)
+        qemu_get_be32s(f, &s->memc_reg[i]);
+
+    return 0;
+}
+
+struct s3c24xx_memc_state_s *
+s3c24xx_memc_init(target_phys_addr_t base_addr)
+{
+    /* Memory controller is simple SDRAM control. As SDRAM is emulated and
+     * requires no setup the emulation needs to be nothing more than memory
+     * backing the registers.
+     *
+     * There are 13 registers, each 4 bytes.
+     */
+    struct s3c24xx_memc_state_s *s = qemu_mallocz(sizeof(struct s3c24xx_memc_state_s));
+
+    int tag;
+    tag = cpu_register_io_memory(0, s3c24xx_memc_read, s3c24xx_memc_write, s);
+    cpu_register_physical_memory(base_addr, 13 * 4, tag);
+    register_savevm("s3c24xx_memc", 0, 0, s3c24xx_memc_save, s3c24xx_memc_load, s);
+
+    return s;
+}
-- 
1.6.0.4