[Qemu-devel] [PATCH 06/16] Peripheral driver for S3C SOC timers.

[Vincent Sanders <vince@simtec.co.uk>]

Signed-off-by: Vincent Sanders <vince@simtec.co.uk>
---
 Makefile.target     |    2 +-
 hw/s3c2410x.c       |    6 ++
 hw/s3c2440.c        |    6 ++
 hw/s3c24xx.h        |    4 +
 hw/s3c24xx_timers.c |  206 +++++++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 223 insertions(+), 1 deletions(-)
 create mode 100644 hw/s3c24xx_timers.c

diff --git a/Makefile.target b/Makefile.target
index d08bb36..81fbc34 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -648,7 +648,7 @@ OBJS+= omap_sx1.o palm.o tsc210x.o
 OBJS+= nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o
 OBJS+= mst_fpga.o mainstone.o
 OBJS+= musicpal.o pflash_cfi02.o
-OBJS+= s3c24xx_memc.o s3c24xx_irq.o s3c24xx_clkcon.o
+OBJS+= s3c24xx_memc.o s3c24xx_irq.o s3c24xx_clkcon.o s3c24xx_timers.o
 OBJS+= s3c2410x.o s3c2440.o
 OBJS+= framebuffer.o
 OBJS+= syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
diff --git a/hw/s3c2410x.c b/hw/s3c2410x.c
index fe685e8..d61abe2 100644
--- a/hw/s3c2410x.c
+++ b/hw/s3c2410x.c
@@ -27,6 +27,9 @@
 /* Clock control */
 #define CPU_S3C2410X_CLKCON_BASE (CPU_S3C2410X_PERIPHERAL + 0xC000000)
 
+/* Timer controller */
+#define CPU_S3C2410X_TIMERS_BASE (CPU_S3C2410X_PERIPHERAL + 0x11000000)
+
 /* Initialise a Samsung S3C2410X SOC ARM core and internal peripherals. */
 S3CState *
 s3c2410x_init(int sdram_size)
@@ -57,5 +60,8 @@ s3c2410x_init(int sdram_size)
     /* Clock and power control */
     s->clkcon = s3c24xx_clkcon_init(s, CPU_S3C2410X_CLKCON_BASE, 12000000);
 
+    /* Timer controller */
+    s->timers = s3c24xx_timers_init(s, CPU_S3C2410X_TIMERS_BASE, 0, 12000000);
+
     return s;
 }
diff --git a/hw/s3c2440.c b/hw/s3c2440.c
index b79451e..1e947df 100644
--- a/hw/s3c2440.c
+++ b/hw/s3c2440.c
@@ -27,6 +27,9 @@
 /* Clock control */
 #define CPU_S3C2440_CLKCON_BASE (CPU_S3C2440_PERIPHERAL + 0xC000000)
 
+/* Timer controller */
+#define CPU_S3C2440_TIMERS_BASE (CPU_S3C2440_PERIPHERAL + 0x11000000)
+
 /* Initialise a Samsung S3C2440 SOC ARM core and internal peripherals. */
 S3CState *
 s3c2440_init(int sdram_size)
@@ -55,5 +58,8 @@ s3c2440_init(int sdram_size)
     /* Clock and power control */
     s->clkcon = s3c24xx_clkcon_init(s, CPU_S3C2440_CLKCON_BASE, 12000000);
 
+    /* Timer controller */
+    s->timers = s3c24xx_timers_init(s, CPU_S3C2440_TIMERS_BASE, 0, 12000000);
+
     return s;
 }
diff --git a/hw/s3c24xx.h b/hw/s3c24xx.h
index 000c9ba..9cc7f37 100644
--- a/hw/s3c24xx.h
+++ b/hw/s3c24xx.h
@@ -24,6 +24,8 @@ typedef struct S3CState_s {
     /* Clock and power control */
     struct s3c24xx_clkcon_state_s *clkcon;
 
+    /* timer controller */
+    struct s3c24xx_timers_state_s *timers;
 } S3CState;
 
 
@@ -39,5 +41,7 @@ qemu_irq s3c24xx_get_irq(struct s3c24xx_irq_state_s *s, int inum);
 /* initialise clock controller */
 struct s3c24xx_clkcon_state_s *s3c24xx_clkcon_init(S3CState *soc, target_phys_addr_t base_addr, uint32_t ref_freq);
 
+/* initialise timer controller */
+struct s3c24xx_timers_state_s *s3c24xx_timers_init(S3CState *soc, target_phys_addr_t base_addr, uint32_t tclk0, uint32_t tclk1);
 
 #endif /* S3C24XX_H */
diff --git a/hw/s3c24xx_timers.c b/hw/s3c24xx_timers.c
new file mode 100644
index 0000000..b1cafbe
--- /dev/null
+++ b/hw/s3c24xx_timers.c
@@ -0,0 +1,206 @@
+/* hw/s3c24xx_timers.c
+ *
+ * Samsung S3C24XX PWM emulation
+ *
+ * Copyright 2009 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+#include "qemu-timer.h"
+
+#include "s3c24xx.h"
+
+/* The S3c24xx timer peripheral has five seperate timers. The first four (0-3)
+ * have physical external connections and can be used for PWM control. The
+ * fifth has no external connection but can generate interrupts because of this
+ * it is almost always used to generate the Operating system clock tick
+ * interrupt.
+ *
+ * The timers can be fed from the peripheral clock (pclk) or from one of two
+ * external inputs (tclk0 and 1). The external inputs are split so tclk0 is
+ * used for timer 0 and 1 and tclk1 feeds the remaining three timers.
+ *
+ * The emulation presented here only iplements the fifth timer (timer 4) as
+ * there is no sensible way to interpret the external physical PWM signals from
+ * timers 0 to 4 yet.
+ *
+ * ticks_per_sec is ticks per second for the qemu clocks
+ * TCLK1 is the assumed input for timer4
+ * Thus, period in ticks of timer4 is:
+ *
+ * (timer4_period * ticks_per_sec) / TCLK1
+ */
+
+/* Timer configuration 0 */
+#define S3C_TIMERS_TCFG0 0
+/* Timer configuration 1 */
+#define S3C_TIMERS_TCFG1 1
+/* Timer control */
+#define S3C_TIMERS_TCON 2
+/* Timer count buffer 0 */
+#define S3C_TIMERS_TCNTB0 3
+/* Timer compare buffer 0 */
+#define S3C_TIMERS_TCMPB0 4
+/* Timer count observation 0 */
+#define S3C_TIMERS_TCNTO0 5
+/* Timer count buffer 1 */
+#define S3C_TIMERS_TCNTB1 6
+/* Timer compare buffer 1 */
+#define S3C_TIMERS_TCMPB1 7
+/* Timer count observation 1 */
+#define S3C_TIMERS_TCNTO1 8
+/* Timer count buffer 2 */
+#define S3C_TIMERS_TCNTB2 9
+/* Timer compare buffer 2 */
+#define S3C_TIMERS_TCMPB2 10
+/* Timer count observation 2 */
+#define S3C_TIMERS_TCNTO2 11
+/* Timer count buffer 3 */
+#define S3C_TIMERS_TCNTB3 12
+/* Timer compare buffer 3 */
+#define S3C_TIMERS_TCMPB3 13
+/* Timer count observation 3 */
+#define S3C_TIMERS_TCNTO3 14
+/* Timer count buffer 4 */
+#define S3C_TIMERS_TCNTB4 15
+/* Timer count observation 4 */
+#define S3C_TIMERS_TCNTO4 16
+
+/* timer controller state */
+struct s3c24xx_timers_state_s {
+    uint32_t tclk0; /* first timer clock source frequency */
+    uint32_t tclk1; /* second timer clock source frequency */
+
+    uint32_t timers_reg[17]; /* registers */
+
+    /* resources for each timer */
+    QEMUTimer *timer[5];
+    qemu_irq irqs[5];
+    uint32_t timer_reload_value[5];
+    int64_t timer_last_ticked[5];
+
+};
+
+
+static void
+s3c24xx_schedule_timer(struct s3c24xx_timers_state_s *s, int num)
+{
+    s->timers_reg[S3C_TIMERS_TCNTB4] = s->timer_reload_value[num];
+    s->timer_last_ticked[num] = qemu_get_clock(vm_clock);
+    qemu_mod_timer(s->timer[num],
+                   s->timer_last_ticked[num] +
+                   ((s->timer_reload_value[num] * ticks_per_sec) / s->tclk1));
+}
+
+static void
+s3c24xx_timer4_tick(void *opaque)
+{
+    struct s3c24xx_timers_state_s *s = (struct s3c24xx_timers_state_s *)opaque;
+
+    /* set IRQ */
+    qemu_set_irq(s->irqs[4], 1);
+
+    /* if auto reload is set rescedule the next tick */
+    if (s->timers_reg[S3C_TIMERS_TCON] && (1<<22)) {
+        s3c24xx_schedule_timer(s, 4);
+    }
+}
+
+static void
+s3c24xx_timers_write_f(void *opaque, target_phys_addr_t addr_, uint32_t value)
+{
+    struct s3c24xx_timers_state_s *s = (struct s3c24xx_timers_state_s *)opaque;
+    int addr = (addr_ >> 2) & 0x1f;
+
+    s->timers_reg[addr] = value;
+
+    if (addr == S3C_TIMERS_TCON) {
+        if (value & (1 << 21)) {
+            /* Timer4 manual update is set, copy in the reload value */
+            s->timer_reload_value[4] = s->timers_reg[S3C_TIMERS_TCNTB4];
+        } else {
+            /* Timer4 manual update is not set */
+            if (value & (1 << 20)) {
+                /* The timer is supposed to be running so start it  */
+                s3c24xx_schedule_timer(s, 4);
+            }
+        }
+    }
+}
+
+static uint32_t
+s3c24xx_timers_read_f(void *opaque, target_phys_addr_t addr_)
+{
+    struct s3c24xx_timers_state_s *s = (struct s3c24xx_timers_state_s *)opaque;
+    int addr = (addr_ >> 2) & 0x1f;
+
+    if (addr == S3C_TIMERS_TCNTO4 ) {
+        return s->timer_reload_value[4] - (((qemu_get_clock(vm_clock) - s->timer_last_ticked[4]) * s->tclk1) / ticks_per_sec);
+    }
+    return s->timers_reg[addr];
+}
+
+
+static CPUReadMemoryFunc *s3c24xx_timers_read[] = {
+    &s3c24xx_timers_read_f,
+    &s3c24xx_timers_read_f,
+    &s3c24xx_timers_read_f,
+};
+
+static CPUWriteMemoryFunc *s3c24xx_timers_write[] = {
+    &s3c24xx_timers_write_f,
+    &s3c24xx_timers_write_f,
+    &s3c24xx_timers_write_f,
+};
+
+static void s3c24xx_timers_save(QEMUFile *f, void *opaque)
+{
+    struct s3c24xx_timers_state_s *s = (struct s3c24xx_timers_state_s *)opaque;
+    int i;
+
+    for (i = 0; i < 17; i ++)
+        qemu_put_be32s(f, &s->timers_reg[i]);
+}
+
+static int s3c24xx_timers_load(QEMUFile *f, void *opaque, int version_id)
+{
+    struct s3c24xx_timers_state_s *s = (struct s3c24xx_timers_state_s *)opaque;
+    int i;
+
+    for (i = 0; i < 17; i ++)
+        qemu_get_be32s(f, &s->timers_reg[i]);
+
+    return 0;
+}
+
+/* S3c24xx timer initialisation */
+struct s3c24xx_timers_state_s *
+s3c24xx_timers_init(S3CState *soc, target_phys_addr_t base_addr, uint32_t tclk0, uint32_t tclk1)
+{
+    struct s3c24xx_timers_state_s *s;
+    int tag;
+    int i;
+
+    s = qemu_mallocz(sizeof(struct s3c24xx_timers_state_s));
+
+    tag = cpu_register_io_memory(0, s3c24xx_timers_read, s3c24xx_timers_write, s);
+    cpu_register_physical_memory(base_addr, 17 * 4, tag);
+    register_savevm("s3c24xx_timers", 0, 0, s3c24xx_timers_save, s3c24xx_timers_load, s);
+
+    s->tclk0 = tclk0;
+    s->tclk1 = tclk1;
+
+    /* set up per timer values */
+    for (i = 0; i < 5; i++) {
+        s->irqs[i] = s3c24xx_get_irq(soc->irq, 10 + i);
+        s->timer_reload_value[i] = 0;
+        s->timer_last_ticked[i] = 0;
+    }
+
+    s->timer[4] = qemu_new_timer(vm_clock, s3c24xx_timer4_tick, s);
+
+    return s;
+}
-- 
1.6.0.4