From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MA23Z-0000qY-4X for qemu-devel@nongnu.org; Fri, 29 May 2009 09:23:33 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MA23Y-0000q1-AV for qemu-devel@nongnu.org; Fri, 29 May 2009 09:23:32 -0400 Received: from [199.232.76.173] (port=55853 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MA23Y-0000pw-5K for qemu-devel@nongnu.org; Fri, 29 May 2009 09:23:32 -0400 Received: from flounder.pepperfish.net ([87.237.62.181]:56604) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MA23X-0002Fv-Kg for qemu-devel@nongnu.org; Fri, 29 May 2009 09:23:32 -0400 From: Vincent Sanders Date: Fri, 29 May 2009 14:23:25 +0100 Message-Id: <1243603405-12989-2-git-send-email-vince@simtec.co.uk> In-Reply-To: <1243603405-12989-1-git-send-email-vince@simtec.co.uk> References: <1243603405-12989-1-git-send-email-vince@simtec.co.uk> Subject: [Qemu-devel] [PATCH 1/1] Update ARM emulation to be version 4t by default List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Vincent Sanders Update ARM emulation to be version 4t by default and add v5 as a feature. Implementation is very similar to the way the v6 features are presented. Signed-off-by: Vincent Sanders --- target-arm/cpu.h | 2 ++ target-arm/helper.c | 16 ++++++++++++++++ target-arm/translate.c | 16 ++++++++++------ 3 files changed, 28 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index f98655f..61df46e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -331,6 +331,7 @@ enum arm_features { ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ + ARM_FEATURE_V5, ARM_FEATURE_V6, ARM_FEATURE_V6K, ARM_FEATURE_V7, @@ -370,6 +371,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define ARM_CPUID_ARM1026 0x4106a262 #define ARM_CPUID_ARM926 0x41069265 #define ARM_CPUID_ARM946 0x41059461 +#define ARM_CPUID_ARM920T 0x41129200 #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 #define ARM_CPUID_PXA250 0x69052100 diff --git a/target-arm/helper.c b/target-arm/helper.c index 701629a..214cbf1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -37,18 +37,25 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { env->cp15.c0_cpuid = id; switch (id) { + case ARM_CPUID_ARM920T: + env->cp15.c0_cachetype = 0x0d172172; + env->cp15.c1_sys = 0x00000078; + break; case ARM_CPUID_ARM926: + set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_VFP); env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090; env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM946: + set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_MPU); env->cp15.c0_cachetype = 0x0f004006; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_ARM1026: + set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_AUXCR); env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0; @@ -57,6 +64,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_ARM1136_R2: case ARM_CPUID_ARM1136: + set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_VFP); set_feature(env, ARM_FEATURE_AUXCR); @@ -68,6 +76,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_ARM11MPCORE: + set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_VFP); @@ -80,6 +89,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: + set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); @@ -101,6 +111,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */ break; case ARM_CPUID_CORTEXM3: + set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_V7); @@ -108,6 +119,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) set_feature(env, ARM_FEATURE_DIV); break; case ARM_CPUID_ANY: /* For userspace emulation. */ + set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_V6); set_feature(env, ARM_FEATURE_V6K); set_feature(env, ARM_FEATURE_V7); @@ -120,6 +132,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) break; case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: + set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_OMAPCP); env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */ env->cp15.c0_cachetype = 0x5109149; @@ -132,6 +145,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA260: case ARM_CPUID_PXA261: case ARM_CPUID_PXA262: + set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_XSCALE); /* JTAG_ID is ((id << 28) | 0x09265013) */ env->cp15.c0_cachetype = 0xd172172; @@ -143,6 +157,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA270_B1: case ARM_CPUID_PXA270_C0: case ARM_CPUID_PXA270_C5: + set_feature(env, ARM_FEATURE_V5); set_feature(env, ARM_FEATURE_XSCALE); /* JTAG_ID is ((id << 28) | 0x09265013) */ set_feature(env, ARM_FEATURE_IWMMXT); @@ -277,6 +292,7 @@ struct arm_cpu_t { }; static const struct arm_cpu_t arm_cpu_names[] = { + { ARM_CPUID_ARM920T, "arm920t"}, { ARM_CPUID_ARM926, "arm926"}, { ARM_CPUID_ARM946, "arm946"}, { ARM_CPUID_ARM1026, "arm1026"}, diff --git a/target-arm/translate.c b/target-arm/translate.c index adac19a..a294f3a 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -35,6 +35,7 @@ #define GEN_HELPER 1 #include "helpers.h" +#define ENABLE_ARCH_5 arm_feature(env, ARM_FEATURE_V5) #define ENABLE_ARCH_5J 0 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6) #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K) @@ -5995,7 +5996,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) tmp = load_reg(s, rm); gen_bx(s, tmp); } else if (op1 == 3) { - /* clz */ + ARCH(5); /* clz */ rd = (insn >> 12) & 0xf; tmp = load_reg(s, rm); gen_helper_clz(tmp, tmp); @@ -6018,14 +6019,15 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) if (op1 != 1) goto illegal_op; - /* branch link/exchange thumb (blx) */ + ARCH(5); /* branch link/exchange thumb (blx) */ tmp = load_reg(s, rm); tmp2 = new_tmp(); tcg_gen_movi_i32(tmp2, s->pc); store_reg(s, 14, tmp2); gen_bx(s, tmp); break; - case 0x5: /* saturating add/subtract */ + case 0x5: + ARCH(5); /* saturating add/subtract */ rd = (insn >> 12) & 0xf; rn = (insn >> 16) & 0xf; tmp = load_reg(s, rm); @@ -6039,16 +6041,18 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) dead_tmp(tmp2); store_reg(s, rd, tmp); break; - case 7: /* bkpt */ + case 7: + ARCH(5); /* bkpt */ gen_set_condexec(s); gen_set_pc_im(s->pc - 4); gen_exception(EXCP_BKPT); s->is_jmp = DISAS_JUMP; break; - case 0x8: /* signed multiply */ + case 0x8: case 0xa: case 0xc: case 0xe: + ARCH(5); /* signed multiply */ rs = (insn >> 8) & 0xf; rn = (insn >> 12) & 0xf; rd = (insn >> 16) & 0xf; @@ -7099,7 +7103,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) if (insn & (1 << 22)) { /* Other load/store, table branch. */ if (insn & 0x01200000) { - /* Load/store doubleword. */ + ARCH(5); /* Load/store doubleword. */ if (rn == 15) { addr = new_tmp(); tcg_gen_movi_i32(addr, s->pc & ~3); -- 1.6.0.4