From: Laurent Vivier <laurent@vivier.eu>
To: qemu-devel@nongnu.org
Cc: Andreas Schwab <schwab@linux-m68k.org>,
Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PATCH 14/17] m68k: add "byte", "word" and memory rotate.
Date: Sat, 30 May 2009 00:41:58 +0200 [thread overview]
Message-ID: <1243636921-23054-15-git-send-email-laurent@vivier.eu> (raw)
In-Reply-To: <1243636921-23054-14-git-send-email-laurent@vivier.eu>
Add rotate_im, rotate8_im, rotate16_im, rotate_reg, rotate8_reg, rotate16_reg,
rotate_mem and attach them to M68000 feature.
Signed-off-by: Andreas Schwab <schwab@linux-m68k.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target-m68k/exec.h | 4 +
target-m68k/helper.c | 149 ++++++++++++++++++++++++++++++++++
target-m68k/helpers.h | 12 +++
target-m68k/translate.c | 205 +++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 370 insertions(+), 0 deletions(-)
diff --git a/target-m68k/exec.h b/target-m68k/exec.h
index 3a86b1f..6f63cd8 100644
--- a/target-m68k/exec.h
+++ b/target-m68k/exec.h
@@ -29,6 +29,10 @@ register uint32_t T0 asm(AREG1);
#include "cpu.h"
#include "exec-all.h"
+extern const uint8_t rox8_table[64];
+extern const uint8_t rox16_table[64];
+extern const uint8_t rox32_table[64];
+
static inline void env_to_regs(void)
{
}
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index f15902a..92c7621 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -62,6 +62,42 @@ static m68k_def_t m68k_cpu_defs[] = {
{NULL, 0},
};
+/* modulo 33 table */
+const uint8_t rox32_table[64] = {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32, 0, 1, 2, 3, 4, 5, 6,
+ 7, 8, 9,10,11,12,13,14,
+ 15,16,17,18,19,20,21,22,
+ 23,24,25,26,27,28,29,30,
+};
+
+/* modulo 17 table */
+const uint8_t rox16_table[64] = {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9,10,11,12,13,14,15,
+ 16, 0, 1, 2, 3, 4, 5, 6,
+ 7, 8, 9,10,11,12,13,14,
+ 15,16, 0, 1, 2, 3, 4, 5,
+ 6, 7, 8, 9,10,11,12,13,
+ 14,15,16, 0, 1, 2, 3, 4,
+ 5, 6, 7, 8, 9,10,11,12,
+};
+
+/* modulo 9 table */
+const uint8_t rox8_table[64] = {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 0, 1, 2, 3, 4, 5, 6,
+ 7, 8, 0, 1, 2, 3, 4, 5,
+ 6, 7, 8, 0, 1, 2, 3, 4,
+ 5, 6, 7, 8, 0, 1, 2, 3,
+ 4, 5, 6, 7, 8, 0, 1, 2,
+ 3, 4, 5, 6, 7, 8, 0, 1,
+ 2, 3, 4, 5, 6, 7, 8, 0,
+};
+
void m68k_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
{
unsigned int i;
@@ -627,6 +663,119 @@ HELPER_SAR(int8_t, 8)
HELPER_SAR(int16_t, 16)
HELPER_SAR(int32_t, 32)
+#define HELPER_ROL(type, bits) \
+uint32_t HELPER(glue(glue(rol,bits),_cc))(CPUState *env, uint32_t val, uint32_t shift) \
+{ \
+ type result; \
+ uint32_t flags; \
+ int count = shift & (bits - 1); \
+ if (count) \
+ result = ((type)val << count) | ((type)val >> (bits - count)); \
+ else \
+ result = (type)val; \
+ flags = 0; \
+ if (result == 0) \
+ flags |= CCF_Z; \
+ if (result & (1 << (bits - 1))) \
+ flags |= CCF_N; \
+ if (shift && result & 1) \
+ flags |= CCF_C; \
+ env->cc_dest = flags; \
+ return result; \
+}
+
+HELPER_ROL(uint8_t, 8)
+HELPER_ROL(uint16_t, 16)
+HELPER_ROL(uint32_t, 32)
+
+#define HELPER_ROR(type, bits) \
+uint32_t HELPER(glue(glue(ror,bits),_cc))(CPUState *env, uint32_t val, uint32_t shift) \
+{ \
+ type result; \
+ uint32_t flags; \
+ int count = shift & (bits - 1); \
+ if (count) \
+ result = ((type)val >> count) | ((type)val << (bits - count)); \
+ else \
+ result = (type)val; \
+ flags = 0; \
+ if (result == 0) \
+ flags |= CCF_Z; \
+ if (result & (1 << (bits - 1))) \
+ flags |= CCF_N; \
+ if (shift && result & (1 << (bits - 1))) \
+ flags |= CCF_C; \
+ env->cc_dest = flags; \
+ return result; \
+}
+
+HELPER_ROR(uint8_t, 8)
+HELPER_ROR(uint16_t, 16)
+HELPER_ROR(uint32_t, 32)
+
+#define HELPER_ROXR(type, bits) \
+uint32_t HELPER(glue(glue(roxr,bits),_cc))(CPUState *env, uint32_t val, uint32_t shift) \
+{ \
+ type result; \
+ uint32_t flags; \
+ int count = shift; \
+ if (bits == 8) count = rox8_table[count]; \
+ if (bits == 16) count = rox16_table[count]; \
+ if (bits == 32) count = rox32_table[count]; \
+ if (count) { \
+ result = ((type)val >> count) | ((type)env->cc_x << (bits - count)); \
+ if (count > 1) \
+ result |= (type)val << (bits + 1 - count); \
+ env->cc_x = ((type)val >> (count - 1)) & 1; \
+ } else \
+ result = (type)val; \
+ flags = 0; \
+ if (result == 0) \
+ flags |= CCF_Z; \
+ if (result & (1 << (bits - 1))) \
+ flags |= CCF_N; \
+ if (env->cc_x) \
+ flags |= CCF_C; \
+ env->cc_dest = flags; \
+ return result; \
+}
+
+HELPER_ROXR(uint8_t, 8)
+HELPER_ROXR(uint16_t, 16)
+HELPER_ROXR(uint32_t, 32)
+
+#define HELPER_ROXL(type, bits) \
+uint32_t HELPER(glue(glue(roxl,bits),_cc))(CPUState *env, uint32_t val, uint32_t shift) \
+{ \
+ type result; \
+ uint32_t flags; \
+ int count; \
+ count = shift; \
+ if (bits == 8) count = rox8_table[count]; \
+ if (bits == 16) count = rox16_table[count]; \
+ if (bits == 32) count = rox32_table[count]; \
+ if (count) { \
+ result = ((type)val << count) | ((type)env->cc_x << (count - 1)); \
+ if (count > 1) \
+ result |= (type)val >> (bits + 1 - count); \
+ env->cc_x = ((type)val >> (bits - count)) & 1; \
+ } else \
+ result = (type)val; \
+ flags = 0; \
+ if (result == 0) \
+ flags |= CCF_Z; \
+ if (result & (1 << (bits - 1))) \
+ flags |= CCF_N; \
+ if (env->cc_x) \
+ flags |= CCF_C; \
+ env->cc_dest = flags; \
+ return result; \
+}
+
+HELPER_ROXL(uint8_t, 8)
+HELPER_ROXL(uint16_t, 16)
+HELPER_ROXL(uint32_t, 32)
+
/* FPU helpers. */
uint32_t HELPER(f64_to_i32)(CPUState *env, float64 val)
{
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index d1993ab..07d1f82 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -22,6 +22,18 @@ DEF_HELPER_3(shr32_cc, i32, env, i32, i32)
DEF_HELPER_3(sar8_cc, i32, env, i32, i32)
DEF_HELPER_3(sar16_cc, i32, env, i32, i32)
DEF_HELPER_3(sar32_cc, i32, env, i32, i32)
+DEF_HELPER_3(rol8_cc, i32, env, i32, i32)
+DEF_HELPER_3(rol16_cc, i32, env, i32, i32)
+DEF_HELPER_3(rol32_cc, i32, env, i32, i32)
+DEF_HELPER_3(ror8_cc, i32, env, i32, i32)
+DEF_HELPER_3(ror16_cc, i32, env, i32, i32)
+DEF_HELPER_3(ror32_cc, i32, env, i32, i32)
+DEF_HELPER_3(roxr8_cc, i32, env, i32, i32)
+DEF_HELPER_3(roxr16_cc, i32, env, i32, i32)
+DEF_HELPER_3(roxr32_cc, i32, env, i32, i32)
+DEF_HELPER_3(roxl8_cc, i32, env, i32, i32)
+DEF_HELPER_3(roxl16_cc, i32, env, i32, i32)
+DEF_HELPER_3(roxl32_cc, i32, env, i32, i32)
DEF_HELPER_2(xflag_lt, i32, i32, i32)
DEF_HELPER_2(set_sr, void, env, i32)
DEF_HELPER_3(movec, void, env, i32, i32)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 10b67e5..17ab88c 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2192,6 +2192,204 @@ DISAS_INSN(shift_mem)
DEST_EA(insn, OS_WORD, dest, &addr);
}
+DISAS_INSN(rotate_im)
+{
+ TCGv reg;
+ TCGv shift;
+ int tmp;
+
+ reg = DREG(insn, 0);
+ tmp = (insn >> 9) & 7;
+ if (tmp == 0)
+ tmp = 8;
+ shift = tcg_const_i32(tmp);
+ if (insn & 8) {
+ if (insn & 0x100) {
+ gen_helper_rol32_cc(reg, cpu_env, reg, shift);
+ } else {
+ gen_helper_ror32_cc(reg, cpu_env, reg, shift);
+ }
+ } else {
+ if (insn & 0x100) {
+ gen_helper_roxl32_cc(reg, cpu_env, reg, shift);
+ } else {
+ gen_helper_roxr32_cc(reg, cpu_env, reg, shift);
+ }
+ }
+ s->cc_op = CC_OP_FLAGS;
+}
+
+DISAS_INSN(rotate8_im)
+{
+ TCGv reg;
+ TCGv dest;
+ TCGv shift;
+ int tmp;
+
+ reg = DREG(insn, 0);
+ tmp = (insn >> 9) & 7;
+ if (tmp == 0)
+ tmp = 8;
+ dest = tcg_temp_new_i32();
+ shift = tcg_const_i32(tmp);
+ if (insn & 8) {
+ if (insn & 0x100) {
+ gen_helper_rol8_cc(dest, cpu_env, reg, shift);
+ } else {
+ gen_helper_ror8_cc(dest, cpu_env, reg, shift);
+ }
+ } else {
+ if (insn & 0x100) {
+ gen_helper_roxl8_cc(dest, cpu_env, reg, shift);
+ } else {
+ gen_helper_roxr8_cc(dest, cpu_env, reg, shift);
+ }
+ }
+ s->cc_op = CC_OP_FLAGS;
+ gen_partset_reg(OS_BYTE, reg, dest);
+}
+
+DISAS_INSN(rotate16_im)
+{
+ TCGv reg;
+ TCGv dest;
+ TCGv shift;
+ int tmp;
+
+ reg = DREG(insn, 0);
+ tmp = (insn >> 9) & 7;
+ if (tmp == 0)
+ tmp = 8;
+ dest = tcg_temp_new_i32();
+ shift = tcg_const_i32(tmp);
+ if (insn & 8) {
+ if (insn & 0x100) {
+ gen_helper_rol16_cc(dest, cpu_env, reg, shift);
+ } else {
+ gen_helper_ror16_cc(dest, cpu_env, reg, shift);
+ }
+ } else {
+ if (insn & 0x100) {
+ gen_helper_roxl16_cc(dest, cpu_env, reg, shift);
+ } else {
+ gen_helper_roxr16_cc(dest, cpu_env, reg, shift);
+ }
+ }
+ s->cc_op = CC_OP_FLAGS;
+ gen_partset_reg(OS_WORD, reg, dest);
+}
+
+DISAS_INSN(rotate_reg)
+{
+ TCGv reg;
+ TCGv src;
+ TCGv tmp;
+
+ reg = DREG(insn, 0);
+ src = DREG(insn, 9);
+ tmp = tcg_temp_new_i32();
+ tcg_gen_andi_i32(tmp, src, 63);
+ if (insn & 8) {
+ if (insn & 0x100) {
+ gen_helper_rol32_cc(reg, cpu_env, reg, tmp);
+ } else {
+ gen_helper_ror32_cc(reg, cpu_env, reg, tmp);
+ }
+ } else {
+ if (insn & 0x100) {
+ gen_helper_roxl32_cc(reg, cpu_env, reg, tmp);
+ } else {
+ gen_helper_roxr32_cc(reg, cpu_env, reg, tmp);
+ }
+ }
+ s->cc_op = CC_OP_FLAGS;
+}
+
+DISAS_INSN(rotate8_reg)
+{
+ TCGv reg;
+ TCGv src;
+ TCGv dest;
+ TCGv tmp;
+
+ reg = DREG(insn, 0);
+ src = DREG(insn, 9);
+ tmp = tcg_temp_new_i32();
+ tcg_gen_andi_i32(tmp, src, 63);
+ dest = tcg_temp_new_i32();
+ if (insn & 8) {
+ if (insn & 0x100) {
+ gen_helper_rol8_cc(dest, cpu_env, reg, tmp);
+ } else {
+ gen_helper_ror8_cc(dest, cpu_env, reg, tmp);
+ }
+ } else {
+ if (insn & 0x100) {
+ gen_helper_roxl8_cc(dest, cpu_env, reg, tmp);
+ } else {
+ gen_helper_roxr8_cc(dest, cpu_env, reg, tmp);
+ }
+ }
+ s->cc_op = CC_OP_FLAGS;
+ gen_partset_reg(OS_BYTE, reg, dest);
+}
+
+DISAS_INSN(rotate16_reg)
+{
+ TCGv reg;
+ TCGv src;
+ TCGv dest;
+ TCGv tmp;
+
+ reg = DREG(insn, 0);
+ src = DREG(insn, 9);
+ tmp = tcg_temp_new_i32();
+ tcg_gen_andi_i32(tmp, src, 63);
+ dest = tcg_temp_new_i32();
+ if (insn & 8) {
+ if (insn & 0x100) {
+ gen_helper_rol16_cc(dest, cpu_env, reg, tmp);
+ } else {
+ gen_helper_ror16_cc(dest, cpu_env, reg, tmp);
+ }
+ } else {
+ if (insn & 0x100) {
+ gen_helper_roxl16_cc(dest, cpu_env, reg, tmp);
+ } else {
+ gen_helper_roxr16_cc(dest, cpu_env, reg, tmp);
+ }
+ }
+ s->cc_op = CC_OP_FLAGS;
+ gen_partset_reg(OS_WORD, reg, dest);
+}
+
+DISAS_INSN(rotate_mem)
+{
+ TCGv src;
+ TCGv dest;
+ TCGv addr;
+ TCGv shift;
+
+ SRC_EA(src, OS_WORD, 0, &addr);
+ dest = tcg_temp_new_i32();
+ shift = tcg_const_i32(1);
+ if (insn & 8) {
+ if (insn & 0x100) {
+ gen_helper_rol16_cc(dest, cpu_env, src, shift);
+ } else {
+ gen_helper_ror16_cc(dest, cpu_env, src, shift);
+ }
+ } else {
+ if (insn & 0x100) {
+ gen_helper_roxl16_cc(dest, cpu_env, src, shift);
+ } else {
+ gen_helper_roxr16_cc(dest, cpu_env, src, shift);
+ }
+ }
+ s->cc_op = CC_OP_FLAGS;
+ DEST_EA(insn, OS_WORD, dest, &addr);
+}
+
DISAS_INSN(ff1)
{
TCGv reg;
@@ -3327,6 +3525,13 @@ void register_m68k_insns (CPUM68KState *env)
INSN(shift16_reg, e060, f0f0, M68000);
INSN(shift_reg, e0a0, f0f0, M68000);
INSN(shift_mem, e0c0, fcc0, M68000);
+ INSN(rotate_im, e090, f0f0, M68000);
+ INSN(rotate8_im, e010, f0f0, M68000);
+ INSN(rotate16_im, e050, f0f0, M68000);
+ INSN(rotate_reg, e0b0, f0f0, M68000);
+ INSN(rotate8_reg, e030, f0f0, M68000);
+ INSN(rotate16_reg,e070, f0f0, M68000);
+ INSN(rotate_mem, e4c0, fcc0, M68000);
INSN(undef_fpu, f000, f000, CF_ISA_A);
INSN(undef_fpu, f000, f000, M68000);
INSN(fpu, f200, ffc0, CF_FPU);
--
1.5.6.5
next prev parent reply other threads:[~2009-05-29 22:42 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-29 22:41 [Qemu-devel] [PATCH 00/17] m68k: add partial Motorola 680x0 support Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 01/17] m68k: Replace gen_im32() by tcg_const_i32() Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 02/17] m68k: add tcg_gen_debug_insn_start() Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 03/17] m68k: define m680x0 CPUs and features Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 04/17] m68k: add missing accessing modes for some instructions Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 05/17] m68k: add Motorola 680x0 family common instructions Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 06/17] m68k: add Scc instruction with memory operand Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 07/17] m68k: add DBcc instruction Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 08/17] m68k: modify movem instruction to manage word Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 09/17] m68k: add 64bit divide Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 10/17] m68k: add 32bit and 64bit multiply Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 11/17] m68k: add word data size for suba/adda Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 12/17] m68k: add fpu Laurent Vivier
2009-05-29 22:41 ` [Qemu-devel] [PATCH 13/17] m68k: add "byte", "word" and memory shift Laurent Vivier
2009-05-29 22:41 ` Laurent Vivier [this message]
2009-05-29 22:41 ` [Qemu-devel] [PATCH 15/17] m68k: add bitfield_mem, bitfield_reg Laurent Vivier
2009-05-29 22:42 ` [Qemu-devel] [PATCH 16/17] m68k: add variable offset/width to bitfield_reg/bitfield_mem Laurent Vivier
2009-05-29 22:42 ` [Qemu-devel] [PATCH 17/17] m68k: add cas Laurent Vivier
2009-05-30 13:53 ` [Qemu-devel] " Andreas Schwab
2009-05-30 16:53 ` Laurent Vivier
2009-05-30 22:00 ` [Qemu-devel] Re: [PATCH 07/17] m68k: add DBcc instruction Andreas Schwab
2009-05-30 22:05 ` Laurent Vivier
2009-05-31 2:06 ` [Qemu-devel] [PATCH 04/17] m68k: add missing accessing modes for some instructions Stuart Brady
2009-05-31 9:03 ` Laurent Vivier
2009-05-30 17:31 ` [Qemu-devel] [PATCH 00/17] m68k: add partial Motorola 680x0 support François Revol
2009-09-21 2:56 ` Rob Landley
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