From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MAAmL-0002YR-CG for qemu-devel@nongnu.org; Fri, 29 May 2009 18:42:21 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MAAmE-0002UF-Bq for qemu-devel@nongnu.org; Fri, 29 May 2009 18:42:20 -0400 Received: from [199.232.76.173] (port=44642 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MAAmC-0002TT-HT for qemu-devel@nongnu.org; Fri, 29 May 2009 18:42:12 -0400 Received: from smtp2-g21.free.fr ([212.27.42.2]:38210) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MAAmA-0007L0-O0 for qemu-devel@nongnu.org; Fri, 29 May 2009 18:42:11 -0400 From: Laurent Vivier Date: Sat, 30 May 2009 00:41:58 +0200 Message-Id: <1243636921-23054-15-git-send-email-laurent@vivier.eu> In-Reply-To: <1243636921-23054-14-git-send-email-laurent@vivier.eu> References: <1243636921-23054-1-git-send-email-laurent@vivier.eu> <1243636921-23054-2-git-send-email-laurent@vivier.eu> <1243636921-23054-3-git-send-email-laurent@vivier.eu> <1243636921-23054-4-git-send-email-laurent@vivier.eu> <1243636921-23054-5-git-send-email-laurent@vivier.eu> <1243636921-23054-6-git-send-email-laurent@vivier.eu> <1243636921-23054-7-git-send-email-laurent@vivier.eu> <1243636921-23054-8-git-send-email-laurent@vivier.eu> <1243636921-23054-9-git-send-email-laurent@vivier.eu> <1243636921-23054-10-git-send-email-laurent@vivier.eu> <1243636921-23054-11-git-send-email-laurent@vivier.eu> <1243636921-23054-12-git-send-email-laurent@vivier.eu> <1243636921-23054-13-git-send-email-laurent@vivier.eu> <1243636921-23054-14-git-send-email-laurent@vivier.eu> Subject: [Qemu-devel] [PATCH 14/17] m68k: add "byte", "word" and memory rotate. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Andreas Schwab , Laurent Vivier Add rotate_im, rotate8_im, rotate16_im, rotate_reg, rotate8_reg, rotate16_reg, rotate_mem and attach them to M68000 feature. Signed-off-by: Andreas Schwab Signed-off-by: Laurent Vivier --- target-m68k/exec.h | 4 + target-m68k/helper.c | 149 ++++++++++++++++++++++++++++++++++ target-m68k/helpers.h | 12 +++ target-m68k/translate.c | 205 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 370 insertions(+), 0 deletions(-) diff --git a/target-m68k/exec.h b/target-m68k/exec.h index 3a86b1f..6f63cd8 100644 --- a/target-m68k/exec.h +++ b/target-m68k/exec.h @@ -29,6 +29,10 @@ register uint32_t T0 asm(AREG1); #include "cpu.h" #include "exec-all.h" +extern const uint8_t rox8_table[64]; +extern const uint8_t rox16_table[64]; +extern const uint8_t rox32_table[64]; + static inline void env_to_regs(void) { } diff --git a/target-m68k/helper.c b/target-m68k/helper.c index f15902a..92c7621 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -62,6 +62,42 @@ static m68k_def_t m68k_cpu_defs[] = { {NULL, 0}, }; +/* modulo 33 table */ +const uint8_t rox32_table[64] = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32, 0, 1, 2, 3, 4, 5, 6, + 7, 8, 9,10,11,12,13,14, + 15,16,17,18,19,20,21,22, + 23,24,25,26,27,28,29,30, +}; + +/* modulo 17 table */ +const uint8_t rox16_table[64] = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9,10,11,12,13,14,15, + 16, 0, 1, 2, 3, 4, 5, 6, + 7, 8, 9,10,11,12,13,14, + 15,16, 0, 1, 2, 3, 4, 5, + 6, 7, 8, 9,10,11,12,13, + 14,15,16, 0, 1, 2, 3, 4, + 5, 6, 7, 8, 9,10,11,12, +}; + +/* modulo 9 table */ +const uint8_t rox8_table[64] = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 0, 1, 2, 3, 4, 5, 6, + 7, 8, 0, 1, 2, 3, 4, 5, + 6, 7, 8, 0, 1, 2, 3, 4, + 5, 6, 7, 8, 0, 1, 2, 3, + 4, 5, 6, 7, 8, 0, 1, 2, + 3, 4, 5, 6, 7, 8, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 0, +}; + void m68k_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) { unsigned int i; @@ -627,6 +663,119 @@ HELPER_SAR(int8_t, 8) HELPER_SAR(int16_t, 16) HELPER_SAR(int32_t, 32) +#define HELPER_ROL(type, bits) \ +uint32_t HELPER(glue(glue(rol,bits),_cc))(CPUState *env, uint32_t val, uint32_t shift) \ +{ \ + type result; \ + uint32_t flags; \ + int count = shift & (bits - 1); \ + if (count) \ + result = ((type)val << count) | ((type)val >> (bits - count)); \ + else \ + result = (type)val; \ + flags = 0; \ + if (result == 0) \ + flags |= CCF_Z; \ + if (result & (1 << (bits - 1))) \ + flags |= CCF_N; \ + if (shift && result & 1) \ + flags |= CCF_C; \ + env->cc_dest = flags; \ + return result; \ +} + +HELPER_ROL(uint8_t, 8) +HELPER_ROL(uint16_t, 16) +HELPER_ROL(uint32_t, 32) + +#define HELPER_ROR(type, bits) \ +uint32_t HELPER(glue(glue(ror,bits),_cc))(CPUState *env, uint32_t val, uint32_t shift) \ +{ \ + type result; \ + uint32_t flags; \ + int count = shift & (bits - 1); \ + if (count) \ + result = ((type)val >> count) | ((type)val << (bits - count)); \ + else \ + result = (type)val; \ + flags = 0; \ + if (result == 0) \ + flags |= CCF_Z; \ + if (result & (1 << (bits - 1))) \ + flags |= CCF_N; \ + if (shift && result & (1 << (bits - 1))) \ + flags |= CCF_C; \ + env->cc_dest = flags; \ + return result; \ +} + +HELPER_ROR(uint8_t, 8) +HELPER_ROR(uint16_t, 16) +HELPER_ROR(uint32_t, 32) + +#define HELPER_ROXR(type, bits) \ +uint32_t HELPER(glue(glue(roxr,bits),_cc))(CPUState *env, uint32_t val, uint32_t shift) \ +{ \ + type result; \ + uint32_t flags; \ + int count = shift; \ + if (bits == 8) count = rox8_table[count]; \ + if (bits == 16) count = rox16_table[count]; \ + if (bits == 32) count = rox32_table[count]; \ + if (count) { \ + result = ((type)val >> count) | ((type)env->cc_x << (bits - count)); \ + if (count > 1) \ + result |= (type)val << (bits + 1 - count); \ + env->cc_x = ((type)val >> (count - 1)) & 1; \ + } else \ + result = (type)val; \ + flags = 0; \ + if (result == 0) \ + flags |= CCF_Z; \ + if (result & (1 << (bits - 1))) \ + flags |= CCF_N; \ + if (env->cc_x) \ + flags |= CCF_C; \ + env->cc_dest = flags; \ + return result; \ +} + +HELPER_ROXR(uint8_t, 8) +HELPER_ROXR(uint16_t, 16) +HELPER_ROXR(uint32_t, 32) + +#define HELPER_ROXL(type, bits) \ +uint32_t HELPER(glue(glue(roxl,bits),_cc))(CPUState *env, uint32_t val, uint32_t shift) \ +{ \ + type result; \ + uint32_t flags; \ + int count; \ + count = shift; \ + if (bits == 8) count = rox8_table[count]; \ + if (bits == 16) count = rox16_table[count]; \ + if (bits == 32) count = rox32_table[count]; \ + if (count) { \ + result = ((type)val << count) | ((type)env->cc_x << (count - 1)); \ + if (count > 1) \ + result |= (type)val >> (bits + 1 - count); \ + env->cc_x = ((type)val >> (bits - count)) & 1; \ + } else \ + result = (type)val; \ + flags = 0; \ + if (result == 0) \ + flags |= CCF_Z; \ + if (result & (1 << (bits - 1))) \ + flags |= CCF_N; \ + if (env->cc_x) \ + flags |= CCF_C; \ + env->cc_dest = flags; \ + return result; \ +} + +HELPER_ROXL(uint8_t, 8) +HELPER_ROXL(uint16_t, 16) +HELPER_ROXL(uint32_t, 32) + /* FPU helpers. */ uint32_t HELPER(f64_to_i32)(CPUState *env, float64 val) { diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h index d1993ab..07d1f82 100644 --- a/target-m68k/helpers.h +++ b/target-m68k/helpers.h @@ -22,6 +22,18 @@ DEF_HELPER_3(shr32_cc, i32, env, i32, i32) DEF_HELPER_3(sar8_cc, i32, env, i32, i32) DEF_HELPER_3(sar16_cc, i32, env, i32, i32) DEF_HELPER_3(sar32_cc, i32, env, i32, i32) +DEF_HELPER_3(rol8_cc, i32, env, i32, i32) +DEF_HELPER_3(rol16_cc, i32, env, i32, i32) +DEF_HELPER_3(rol32_cc, i32, env, i32, i32) +DEF_HELPER_3(ror8_cc, i32, env, i32, i32) +DEF_HELPER_3(ror16_cc, i32, env, i32, i32) +DEF_HELPER_3(ror32_cc, i32, env, i32, i32) +DEF_HELPER_3(roxr8_cc, i32, env, i32, i32) +DEF_HELPER_3(roxr16_cc, i32, env, i32, i32) +DEF_HELPER_3(roxr32_cc, i32, env, i32, i32) +DEF_HELPER_3(roxl8_cc, i32, env, i32, i32) +DEF_HELPER_3(roxl16_cc, i32, env, i32, i32) +DEF_HELPER_3(roxl32_cc, i32, env, i32, i32) DEF_HELPER_2(xflag_lt, i32, i32, i32) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 10b67e5..17ab88c 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2192,6 +2192,204 @@ DISAS_INSN(shift_mem) DEST_EA(insn, OS_WORD, dest, &addr); } +DISAS_INSN(rotate_im) +{ + TCGv reg; + TCGv shift; + int tmp; + + reg = DREG(insn, 0); + tmp = (insn >> 9) & 7; + if (tmp == 0) + tmp = 8; + shift = tcg_const_i32(tmp); + if (insn & 8) { + if (insn & 0x100) { + gen_helper_rol32_cc(reg, cpu_env, reg, shift); + } else { + gen_helper_ror32_cc(reg, cpu_env, reg, shift); + } + } else { + if (insn & 0x100) { + gen_helper_roxl32_cc(reg, cpu_env, reg, shift); + } else { + gen_helper_roxr32_cc(reg, cpu_env, reg, shift); + } + } + s->cc_op = CC_OP_FLAGS; +} + +DISAS_INSN(rotate8_im) +{ + TCGv reg; + TCGv dest; + TCGv shift; + int tmp; + + reg = DREG(insn, 0); + tmp = (insn >> 9) & 7; + if (tmp == 0) + tmp = 8; + dest = tcg_temp_new_i32(); + shift = tcg_const_i32(tmp); + if (insn & 8) { + if (insn & 0x100) { + gen_helper_rol8_cc(dest, cpu_env, reg, shift); + } else { + gen_helper_ror8_cc(dest, cpu_env, reg, shift); + } + } else { + if (insn & 0x100) { + gen_helper_roxl8_cc(dest, cpu_env, reg, shift); + } else { + gen_helper_roxr8_cc(dest, cpu_env, reg, shift); + } + } + s->cc_op = CC_OP_FLAGS; + gen_partset_reg(OS_BYTE, reg, dest); +} + +DISAS_INSN(rotate16_im) +{ + TCGv reg; + TCGv dest; + TCGv shift; + int tmp; + + reg = DREG(insn, 0); + tmp = (insn >> 9) & 7; + if (tmp == 0) + tmp = 8; + dest = tcg_temp_new_i32(); + shift = tcg_const_i32(tmp); + if (insn & 8) { + if (insn & 0x100) { + gen_helper_rol16_cc(dest, cpu_env, reg, shift); + } else { + gen_helper_ror16_cc(dest, cpu_env, reg, shift); + } + } else { + if (insn & 0x100) { + gen_helper_roxl16_cc(dest, cpu_env, reg, shift); + } else { + gen_helper_roxr16_cc(dest, cpu_env, reg, shift); + } + } + s->cc_op = CC_OP_FLAGS; + gen_partset_reg(OS_WORD, reg, dest); +} + +DISAS_INSN(rotate_reg) +{ + TCGv reg; + TCGv src; + TCGv tmp; + + reg = DREG(insn, 0); + src = DREG(insn, 9); + tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, src, 63); + if (insn & 8) { + if (insn & 0x100) { + gen_helper_rol32_cc(reg, cpu_env, reg, tmp); + } else { + gen_helper_ror32_cc(reg, cpu_env, reg, tmp); + } + } else { + if (insn & 0x100) { + gen_helper_roxl32_cc(reg, cpu_env, reg, tmp); + } else { + gen_helper_roxr32_cc(reg, cpu_env, reg, tmp); + } + } + s->cc_op = CC_OP_FLAGS; +} + +DISAS_INSN(rotate8_reg) +{ + TCGv reg; + TCGv src; + TCGv dest; + TCGv tmp; + + reg = DREG(insn, 0); + src = DREG(insn, 9); + tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, src, 63); + dest = tcg_temp_new_i32(); + if (insn & 8) { + if (insn & 0x100) { + gen_helper_rol8_cc(dest, cpu_env, reg, tmp); + } else { + gen_helper_ror8_cc(dest, cpu_env, reg, tmp); + } + } else { + if (insn & 0x100) { + gen_helper_roxl8_cc(dest, cpu_env, reg, tmp); + } else { + gen_helper_roxr8_cc(dest, cpu_env, reg, tmp); + } + } + s->cc_op = CC_OP_FLAGS; + gen_partset_reg(OS_BYTE, reg, dest); +} + +DISAS_INSN(rotate16_reg) +{ + TCGv reg; + TCGv src; + TCGv dest; + TCGv tmp; + + reg = DREG(insn, 0); + src = DREG(insn, 9); + tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, src, 63); + dest = tcg_temp_new_i32(); + if (insn & 8) { + if (insn & 0x100) { + gen_helper_rol16_cc(dest, cpu_env, reg, tmp); + } else { + gen_helper_ror16_cc(dest, cpu_env, reg, tmp); + } + } else { + if (insn & 0x100) { + gen_helper_roxl16_cc(dest, cpu_env, reg, tmp); + } else { + gen_helper_roxr16_cc(dest, cpu_env, reg, tmp); + } + } + s->cc_op = CC_OP_FLAGS; + gen_partset_reg(OS_WORD, reg, dest); +} + +DISAS_INSN(rotate_mem) +{ + TCGv src; + TCGv dest; + TCGv addr; + TCGv shift; + + SRC_EA(src, OS_WORD, 0, &addr); + dest = tcg_temp_new_i32(); + shift = tcg_const_i32(1); + if (insn & 8) { + if (insn & 0x100) { + gen_helper_rol16_cc(dest, cpu_env, src, shift); + } else { + gen_helper_ror16_cc(dest, cpu_env, src, shift); + } + } else { + if (insn & 0x100) { + gen_helper_roxl16_cc(dest, cpu_env, src, shift); + } else { + gen_helper_roxr16_cc(dest, cpu_env, src, shift); + } + } + s->cc_op = CC_OP_FLAGS; + DEST_EA(insn, OS_WORD, dest, &addr); +} + DISAS_INSN(ff1) { TCGv reg; @@ -3327,6 +3525,13 @@ void register_m68k_insns (CPUM68KState *env) INSN(shift16_reg, e060, f0f0, M68000); INSN(shift_reg, e0a0, f0f0, M68000); INSN(shift_mem, e0c0, fcc0, M68000); + INSN(rotate_im, e090, f0f0, M68000); + INSN(rotate8_im, e010, f0f0, M68000); + INSN(rotate16_im, e050, f0f0, M68000); + INSN(rotate_reg, e0b0, f0f0, M68000); + INSN(rotate8_reg, e030, f0f0, M68000); + INSN(rotate16_reg,e070, f0f0, M68000); + INSN(rotate_mem, e4c0, fcc0, M68000); INSN(undef_fpu, f000, f000, CF_ISA_A); INSN(undef_fpu, f000, f000, M68000); INSN(fpu, f200, ffc0, CF_FPU); -- 1.5.6.5