* [Qemu-devel] [PATCH] SH4: Added "TLB Invalidate Bit" management to MMUCR register
@ 2009-05-08 13:30 Lionel Landwerlin
2009-05-08 19:08 ` Lionel Landwerlin
0 siblings, 1 reply; 3+ messages in thread
From: Lionel Landwerlin @ 2009-05-08 13:30 UTC (permalink / raw)
To: qemu-devel
SH4: Added "TLB Invalidate Bit" management to MMUCR register
Signed-off-by: Lionel Landwerlin <lionel.landwerlin@openwide.fr>
---
hw/sh7750.c | 5 +++++
target-sh4/cpu.h | 2 ++
target-sh4/helper.c | 13 ++++++++++++-
3 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 423c43f..718ad53 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -397,6 +397,11 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
portb_changed(s, temp);
return;
case SH7750_MMUCR_A7:
+ if (s->cpu->mmucr & MMUCR_TLB_INVALIDATE)
+ {
+ cpu_sh4_tlbs_invalidate(s->cpu);
+ mem_value |= ~MMUCR_TLB_INVALIDATE;
+ }
s->cpu->mmucr = mem_value;
return;
case SH7750_PTEH_A7:
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index e597f65..bf62e63 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -171,6 +171,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
uint32_t mem_value);
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
+void cpu_sh4_tlbs_invalidate (CPUSH4State * env);
static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
{
@@ -222,6 +223,7 @@ enum {
/* MMU control register */
#define MMUCR 0x1F000010
#define MMUCR_AT (1<<0)
+#define MMUCR_TLB_INVALIDATE (1<<2)
#define MMUCR_SV (1<<8)
#define MMUCR_URC_BITS (6)
#define MMUCR_URC_OFFSET (10)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index d8e08e3..979ec70 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -631,7 +631,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
if (needs_tlb_flush)
tlb_flush_page(s, vpn << 10);
-
+
} else {
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
@@ -694,4 +694,15 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
return 0;
}
+void cpu_sh4_tlbs_invalidate (CPUSH4State * env)
+{
+ int i;
+
+ for (i = 0 ; i < ITLB_SIZE ; i++)
+ env->itlb[i].v = 0;
+
+ for (i = 0 ; i < UTLB_SIZE ; i++)
+ env->utlb[i].v = 0;
+}
+
#endif
--
1.6.2.4
--
Lionel Landwerlin <lionel.landwerlin@openwide.fr>
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] SH4: Added "TLB Invalidate Bit" management to MMUCR register
2009-05-08 13:30 [Qemu-devel] [PATCH] SH4: Added "TLB Invalidate Bit" management to MMUCR register Lionel Landwerlin
@ 2009-05-08 19:08 ` Lionel Landwerlin
2009-05-30 22:10 ` Lionel Landwerlin
0 siblings, 1 reply; 3+ messages in thread
From: Lionel Landwerlin @ 2009-05-08 19:08 UTC (permalink / raw)
To: qemu-devel
SH4: Added "TLB Invalidate Bit" management to MMUCR register
Renamed MMUCR_TLB_INVALIDATE to MMUCR_TI (just like datasheet).
Signed-off-by: Lionel Landwerlin <lionel.landwerlin@openwide.fr>
---
hw/sh7750.c | 5 +++++
target-sh4/cpu.h | 2 ++
target-sh4/helper.c | 13 ++++++++++++-
3 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 423c43f..f9e482e 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -397,6 +397,11 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
portb_changed(s, temp);
return;
case SH7750_MMUCR_A7:
+ if (s->cpu->mmucr & MMUCR_TI)
+ {
+ cpu_sh4_tlbs_invalidate(s->cpu);
+ mem_value |= ~MMUCR_TI;
+ }
s->cpu->mmucr = mem_value;
return;
case SH7750_PTEH_A7:
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index e597f65..b6dc694 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -171,6 +171,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
uint32_t mem_value);
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
+void cpu_sh4_tlbs_invalidate (CPUSH4State * env);
static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
{
@@ -222,6 +223,7 @@ enum {
/* MMU control register */
#define MMUCR 0x1F000010
#define MMUCR_AT (1<<0)
+#define MMUCR_TI (1<<2)
#define MMUCR_SV (1<<8)
#define MMUCR_URC_BITS (6)
#define MMUCR_URC_OFFSET (10)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index d8e08e3..979ec70 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -631,7 +631,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
if (needs_tlb_flush)
tlb_flush_page(s, vpn << 10);
-
+
} else {
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
@@ -694,4 +694,15 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
return 0;
}
+void cpu_sh4_tlbs_invalidate (CPUSH4State * env)
+{
+ int i;
+
+ for (i = 0 ; i < ITLB_SIZE ; i++)
+ env->itlb[i].v = 0;
+
+ for (i = 0 ; i < UTLB_SIZE ; i++)
+ env->utlb[i].v = 0;
+}
+
#endif
--
1.6.2.4
--
Lionel Landwerlin <lionel.landwerlin@openwide.fr>
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] SH4: Added "TLB Invalidate Bit" management to MMUCR register
2009-05-08 19:08 ` Lionel Landwerlin
@ 2009-05-30 22:10 ` Lionel Landwerlin
0 siblings, 0 replies; 3+ messages in thread
From: Lionel Landwerlin @ 2009-05-30 22:10 UTC (permalink / raw)
To: qemu-devel
Le vendredi 08 mai 2009 à 21:08 +0200, Lionel Landwerlin a écrit :
> SH4: Added "TLB Invalidate Bit" management to MMUCR register
>
ping ?
--
Lionel Landwerlin <lionel.landwerlin@openwide.fr>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2009-05-08 19:08 ` Lionel Landwerlin
2009-05-30 22:10 ` Lionel Landwerlin
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