[Qemu-devel] [PATCH 0/3] m68k: Some FPU enhancements.

[Qemu-devel] [PATCH 0/3] m68k: Some FPU enhancements.

[Laurent Vivier]

This series of patch is needed to be able to run "find".

"find" is using some FPU instructions (who knows why ?), and this series of patches adds the missing features.

[PATCH 1/3] m68k: allow fpu to manage double single data type.
[PATCH 2/3] m68k: add FScc instruction
[PATCH 3/3] m68k: add single data type to gen_ea

It must be applied after the series I sent yesterday and the patches sent by Andreas to correct some of them.

[Qemu-devel] [PATCH 1/3] m68k: allow fpu to manage double single data type.

[Laurent Vivier]

This patch allows to manage instructions like "fcmpd #2.2, %fp0".
Original function manages only data accessed through an address register.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/translate.c |   71 +++++++++++++++++++++++++----------------------
 1 files changed, 38 insertions(+), 33 deletions(-)

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index ea6b34b..223b296 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3115,40 +3115,45 @@ DISAS_INSN(fpu)
             goto undef;
         }
         if (opsize == OS_DOUBLE) {
-            tmp32 = tcg_temp_new_i32();
-            tcg_gen_mov_i32(tmp32, AREG(insn, 0));
-            switch ((insn >> 3) & 7) {
-            case 2:
-            case 3:
-                break;
-            case 4:
-                tcg_gen_addi_i32(tmp32, tmp32, -8);
-                break;
-            case 5:
-                offset = ldsw_code(s->pc);
-                s->pc += 2;
-                tcg_gen_addi_i32(tmp32, tmp32, offset);
-                break;
-            case 7:
-                offset = ldsw_code(s->pc);
-                offset += s->pc - 2;
-                s->pc += 2;
-                tcg_gen_addi_i32(tmp32, tmp32, offset);
-                break;
-            default:
-                goto undef;
-            }
-            src = gen_load64(s, tmp32);
-            switch ((insn >> 3) & 7) {
-            case 3:
-                tcg_gen_addi_i32(tmp32, tmp32, 8);
-                tcg_gen_mov_i32(AREG(insn, 0), tmp32);
-                break;
-            case 4:
-                tcg_gen_mov_i32(AREG(insn, 0), tmp32);
-                break;
+            if ((insn & 7) == 4) {
+                src = gen_load64(s, tcg_const_i32(s->pc));
+                s->pc += 8;
+            } else {
+                tmp32 = tcg_temp_new_i32();
+                tcg_gen_mov_i32(tmp32, AREG(insn, 0));
+                switch ((insn >> 3) & 7) {
+                case 2:
+                case 3:
+                    break;
+                case 4:
+                    tcg_gen_addi_i32(tmp32, tmp32, -8);
+                    break;
+                case 5:
+                    offset = ldsw_code(s->pc);
+                    s->pc += 2;
+                    tcg_gen_addi_i32(tmp32, tmp32, offset);
+                    break;
+                case 7:
+                    offset = ldsw_code(s->pc);
+                    offset += s->pc - 2;
+                    s->pc += 2;
+                    tcg_gen_addi_i32(tmp32, tmp32, offset);
+                    break;
+                default:
+                    goto undef;
+                }
+                src = gen_load64(s, tmp32);
+                switch ((insn >> 3) & 7) {
+                case 3:
+                    tcg_gen_addi_i32(tmp32, tmp32, 8);
+                    tcg_gen_mov_i32(AREG(insn, 0), tmp32);
+                    break;
+                case 4:
+                    tcg_gen_mov_i32(AREG(insn, 0), tmp32);
+                    break;
+                }
+                tcg_temp_free_i32(tmp32);
             }
-            tcg_temp_free_i32(tmp32);
         } else {
             SRC_EA(tmp32, opsize, 1, NULL);
             src = tcg_temp_new_i64();
-- 
1.5.6.5

[Qemu-devel] [PATCH 2/3] m68k: add FScc instruction

[Laurent Vivier]

This patch allows to manage instructions like "fsge %d0".

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/translate.c |   82 +++++++++++++++++++++++++++++++++++++++--------
 1 files changed, 68 insertions(+), 14 deletions(-)

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 223b296..8e73984 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3259,27 +3259,15 @@ undef:
     disas_undef_fpu(s, insn);
 }
 
-DISAS_INSN(fbcc)
+static void gen_fjmpcc(DisasContext *s, int cond, int l1)
 {
-    uint32_t offset;
-    uint32_t addr;
     TCGv flag;
-    int l1;
 
-    addr = s->pc;
-    offset = ldsw_code(s->pc);
-    s->pc += 2;
-    if (insn & (1 << 6)) {
-        offset = (offset << 16) | lduw_code(s->pc);
-        s->pc += 2;
-    }
-
-    l1 = gen_new_label();
     /* TODO: Raise BSUN exception.  */
     flag = tcg_temp_new();
     gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT);
     /* Jump to l1 if condition is true.  */
-    switch (insn & 0xf) {
+    switch (cond) {
     case 0: /* f */
         break;
     case 1: /* eq (=0) */
@@ -3330,11 +3318,75 @@ DISAS_INSN(fbcc)
         tcg_gen_br(l1);
         break;
     }
+}
+
+DISAS_INSN(fbcc)
+{
+    uint32_t offset;
+    uint32_t addr;
+    int l1;
+
+    addr = s->pc;
+    offset = ldsw_code(s->pc);
+    s->pc += 2;
+    if (insn & (1 << 6)) {
+        offset = (offset << 16) | lduw_code(s->pc);
+        s->pc += 2;
+    }
+
+    l1 = gen_new_label();
+    gen_fjmpcc(s, insn & 0xf, l1);
     gen_jmp_tb(s, 0, s->pc);
     gen_set_label(l1);
     gen_jmp_tb(s, 1, addr + offset);
 }
 
+DISAS_INSN(fscc_mem)
+{
+    int l1, l2;
+    TCGv taddr;
+    TCGv addr;
+    uint16_t ext;
+
+    ext = lduw_code(s->pc);
+    s->pc += 2;
+
+    taddr = gen_lea(s, insn, OS_BYTE);
+    if (IS_NULL_QREG(taddr)) {
+        gen_addr_fault(s);
+        return;
+    }
+    addr = tcg_temp_local_new ();
+    tcg_gen_mov_i32(addr, taddr);
+    l1 = gen_new_label();
+    l2 = gen_new_label();
+    gen_fjmpcc(s, ext & 0xf, l1);
+    gen_store(s, OS_BYTE, addr, tcg_const_i32(0x00));
+    tcg_gen_br(l2);
+    gen_set_label(l1);
+    gen_store(s, OS_BYTE, addr, tcg_const_i32(0xff));
+    gen_set_label(l2);
+    tcg_temp_free(addr);
+}
+
+DISAS_INSN(fscc_reg)
+{
+    int l1;
+    TCGv reg;
+    uint16_t ext;
+
+    ext = lduw_code(s->pc);
+    s->pc += 2;
+    
+    reg = DREG(insn, 0);
+
+    l1 = gen_new_label();
+    tcg_gen_ori_i32(reg, reg, 0x000000ff);
+    gen_fjmpcc(s, ext & 0xf, l1);
+    tcg_gen_andi_i32(reg, reg, 0xffffff00);
+    gen_set_label(l1);
+}
+
 DISAS_INSN(frestore)
 {
     /* TODO: Implement frestore.  */
@@ -3912,6 +3964,8 @@ void register_m68k_insns (CPUM68KState *env)
     INSN(frestore,  f340, ffc0, CF_FPU);
     INSN(fsave,     f340, ffc0, CF_FPU);
     INSN(fpu,       f200, ffc0, FPU);
+    INSN(fscc_mem,  f240, ffc0, FPU);
+    INSN(fscc_reg,  f240, fff8, FPU);
     INSN(fbcc,      f280, ffc0, FPU);
     INSN(frestore,  f340, ffc0, FPU);
     INSN(fsave,     f340, ffc0, FPU);
-- 
1.5.6.5

[Qemu-devel] [PATCH 3/3] m68k: add single data type to gen_ea

[Laurent Vivier]

This patch allows to have instructions like "fcmps #0.1,%fp1".

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/translate.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 8e73984..8740ea0 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -699,6 +699,7 @@ static TCGv gen_ea(DisasContext *s, uint16_t insn, int opsize, TCGv val,
                 s->pc += 2;
                 break;
             case OS_LONG:
+            case OS_SINGLE:
                 offset = read_im32(s);
                 break;
             default:
-- 
1.5.6.5

[Qemu-devel] Re: [PATCH 1/3] m68k: allow fpu to manage double single data type.

[Andreas Schwab]

Laurent Vivier <laurent@vivier.eu> writes:

> +            if ((insn & 7) == 4) {
> +                src = gen_load64(s, tcg_const_i32(s->pc));
> +                s->pc += 8;

This is wrong, it doesn't check that this is indeed a 7.4 addressing
mode, but will match any other mode with register 4.

> +                case 7:
> +                    offset = ldsw_code(s->pc);
> +                    offset += s->pc - 2;
> +                    s->pc += 2;
> +                    tcg_gen_addi_i32(tmp32, tmp32, offset);
> +                    break;

Btw, this is still broken, pc-rel addressing surely does not want the
contents of register a2 added in (and the 68k supports all the indexed
modes as well).  All non-immediate addresses should probably be handled
by gen_lea.

Andreas.

-- 
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756  01D3 44D5 214B 8276 4ED5
"And now for something completely different."

Re: [Qemu-devel] Re: [PATCH 1/3] m68k: allow fpu to manage double single data type.

[Laurent Vivier]

Le dimanche 31 mai 2009 à 14:03 +0200, Andreas Schwab a écrit :
> Laurent Vivier <laurent@vivier.eu> writes:
> 
> > +            if ((insn & 7) == 4) {
> > +                src = gen_load64(s, tcg_const_i32(s->pc));
> > +                s->pc += 8;
> 
> This is wrong, it doesn't check that this is indeed a 7.4 addressing
> mode, but will match any other mode with register 4.
> 
> > +                case 7:
> > +                    offset = ldsw_code(s->pc);
> > +                    offset += s->pc - 2;
> > +                    s->pc += 2;
> > +                    tcg_gen_addi_i32(tmp32, tmp32, offset);
> > +                    break;
> 
> Btw, this is still broken, pc-rel addressing surely does not want the
> contents of register a2 added in (and the 68k supports all the indexed
> modes as well).  All non-immediate addresses should probably be handled
> by gen_lea.

Yes, I agree, I rework this part.

Laurent