From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MAZG0-0007rZ-LH for qemu-devel@nongnu.org; Sat, 30 May 2009 20:50:36 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MAZFv-0007nK-Os for qemu-devel@nongnu.org; Sat, 30 May 2009 20:50:36 -0400 Received: from [199.232.76.173] (port=41550 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MAZFv-0007n7-JL for qemu-devel@nongnu.org; Sat, 30 May 2009 20:50:31 -0400 Received: from smtp2-g21.free.fr ([212.27.42.2]:32777) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MAZFu-00030L-P5 for qemu-devel@nongnu.org; Sat, 30 May 2009 20:50:31 -0400 From: Laurent Vivier Date: Sun, 31 May 2009 02:50:19 +0200 Message-Id: <1243731021-23692-2-git-send-email-laurent@vivier.eu> In-Reply-To: <1243731021-23692-1-git-send-email-laurent@vivier.eu> References: <1243731021-23692-1-git-send-email-laurent@vivier.eu> Subject: [Qemu-devel] [PATCH 1/3] m68k: allow fpu to manage double single data type. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Andreas Schwab , Laurent Vivier This patch allows to manage instructions like "fcmpd #2.2, %fp0". Original function manages only data accessed through an address register. Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 71 +++++++++++++++++++++++++---------------------- 1 files changed, 38 insertions(+), 33 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index ea6b34b..223b296 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3115,40 +3115,45 @@ DISAS_INSN(fpu) goto undef; } if (opsize == OS_DOUBLE) { - tmp32 = tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp32, AREG(insn, 0)); - switch ((insn >> 3) & 7) { - case 2: - case 3: - break; - case 4: - tcg_gen_addi_i32(tmp32, tmp32, -8); - break; - case 5: - offset = ldsw_code(s->pc); - s->pc += 2; - tcg_gen_addi_i32(tmp32, tmp32, offset); - break; - case 7: - offset = ldsw_code(s->pc); - offset += s->pc - 2; - s->pc += 2; - tcg_gen_addi_i32(tmp32, tmp32, offset); - break; - default: - goto undef; - } - src = gen_load64(s, tmp32); - switch ((insn >> 3) & 7) { - case 3: - tcg_gen_addi_i32(tmp32, tmp32, 8); - tcg_gen_mov_i32(AREG(insn, 0), tmp32); - break; - case 4: - tcg_gen_mov_i32(AREG(insn, 0), tmp32); - break; + if ((insn & 7) == 4) { + src = gen_load64(s, tcg_const_i32(s->pc)); + s->pc += 8; + } else { + tmp32 = tcg_temp_new_i32(); + tcg_gen_mov_i32(tmp32, AREG(insn, 0)); + switch ((insn >> 3) & 7) { + case 2: + case 3: + break; + case 4: + tcg_gen_addi_i32(tmp32, tmp32, -8); + break; + case 5: + offset = ldsw_code(s->pc); + s->pc += 2; + tcg_gen_addi_i32(tmp32, tmp32, offset); + break; + case 7: + offset = ldsw_code(s->pc); + offset += s->pc - 2; + s->pc += 2; + tcg_gen_addi_i32(tmp32, tmp32, offset); + break; + default: + goto undef; + } + src = gen_load64(s, tmp32); + switch ((insn >> 3) & 7) { + case 3: + tcg_gen_addi_i32(tmp32, tmp32, 8); + tcg_gen_mov_i32(AREG(insn, 0), tmp32); + break; + case 4: + tcg_gen_mov_i32(AREG(insn, 0), tmp32); + break; + } + tcg_temp_free_i32(tmp32); } - tcg_temp_free_i32(tmp32); } else { SRC_EA(tmp32, opsize, 1, NULL); src = tcg_temp_new_i64(); -- 1.5.6.5