From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MCNDX-0008Sx-EU for qemu-devel@nongnu.org; Thu, 04 Jun 2009 20:23:31 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MCNDS-0008SI-Mr for qemu-devel@nongnu.org; Thu, 04 Jun 2009 20:23:31 -0400 Received: from [199.232.76.173] (port=48121 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MCMRR-0007rB-Sc for qemu-devel@nongnu.org; Thu, 04 Jun 2009 19:33:50 -0400 Received: from mx20.gnu.org ([199.232.41.8]:38919) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MCIyv-00010i-W4 for qemu-devel@nongnu.org; Thu, 04 Jun 2009 15:52:10 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MCIyr-0007NC-JH for qemu-devel@nongnu.org; Thu, 04 Jun 2009 15:52:05 -0400 From: Nathan Froyd Date: Thu, 4 Jun 2009 11:52:00 -0700 Message-Id: <1244141522-21802-6-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1244141522-21802-1-git-send-email-froydnj@codesourcery.com> References: <1244141522-21802-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 5/7] target-ppc: add exceptions for conditional stores List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Nathan Froyd --- target-ppc/cpu.h | 5 +++ target-ppc/translate.c | 71 ++++++++++++++++++++++++++++++++++------------- 2 files changed, 56 insertions(+), 20 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 8d62218..1733a45 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -220,6 +220,7 @@ enum { /* Qemu exceptions: special cases we want to stop translation */ POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ + POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */ }; /* Exceptions error codes */ @@ -566,6 +567,10 @@ struct CPUPPCState { target_ulong reserve_addr; /* Reservation value */ target_ulong reserve_val; + /* Reservation store address */ + target_ulong reserve_ea; + /* Reserved store source register and size */ + target_ulong reserve_info; /* Those ones are used in supervisor mode only */ /* machine state register */ diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 5401434..78094c7 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -3148,24 +3148,49 @@ GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES) tcg_temp_free(t0); } +#if defined(CONFIG_USER_ONLY) +static void gen_conditional_store (DisasContext *ctx, TCGv EA, + int reg, int size) +{ + TCGv t0 = tcg_temp_new(); + uint32_t save_exception = ctx->exception; + + tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea)); + tcg_gen_movi_tl(t0, (size << 5) | reg); + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info)); + tcg_temp_free(t0); + gen_update_nip(ctx, ctx->nip-4); + ctx->exception = POWERPC_EXCP_BRANCH; + gen_exception(ctx, POWERPC_EXCP_STCX); + ctx->exception = save_exception; +} +#endif + /* stwcx. */ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) { - int l1; TCGv t0; gen_set_access_type(ctx, ACCESS_RES); t0 = tcg_temp_local_new(); gen_addr_reg_index(ctx, t0); gen_check_align(ctx, t0, 0x03); - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); - tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); - tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); - l1 = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); - gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); - gen_set_label(l1); - tcg_gen_movi_tl(cpu_reserve, -1); +#if defined(CONFIG_USER_ONLY) + gen_conditional_store(ctx, t0, rS(ctx->opcode), 4); +#else + { + int l1; + + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); + tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); + tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); + l1 = gen_new_label(); + tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); + tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); + gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); + gen_set_label(l1); + tcg_gen_movi_tl(cpu_reserve, -1); + } +#endif tcg_temp_free(t0); } @@ -3188,21 +3213,27 @@ GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B) /* stdcx. */ GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B) { - int l1; TCGv t0; gen_set_access_type(ctx, ACCESS_RES); t0 = tcg_temp_local_new(); gen_addr_reg_index(ctx, t0); gen_check_align(ctx, t0, 0x07); - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); - tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); - tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); - l1 = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); - gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); - gen_set_label(l1); - tcg_gen_movi_tl(cpu_reserve, -1); +#if defined(CONFIG_USER_ONLY) + gen_conditional_store(ctx, t0, rS(ctx->opcode), 8); +#else + { + int l1; + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); + tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); + tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); + l1 = gen_new_label(); + tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); + tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); + gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); + gen_set_label(l1); + tcg_gen_movi_tl(cpu_reserve, -1); + } +#endif tcg_temp_free(t0); } #endif /* defined(TARGET_PPC64) */ -- 1.6.3.2