From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MCNYD-0006Cv-4a for qemu-devel@nongnu.org; Thu, 04 Jun 2009 20:44:53 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MCNY8-00069U-9X for qemu-devel@nongnu.org; Thu, 04 Jun 2009 20:44:52 -0400 Received: from [199.232.76.173] (port=52855 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MCMR8-0006jX-GF for qemu-devel@nongnu.org; Thu, 04 Jun 2009 19:33:30 -0400 Received: from mx20.gnu.org ([199.232.41.8]:40339) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MCJpm-0000UM-Eg for qemu-devel@nongnu.org; Thu, 04 Jun 2009 16:46:46 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MCJpl-0001RO-1r for qemu-devel@nongnu.org; Thu, 04 Jun 2009 16:46:45 -0400 From: Nathan Froyd Date: Thu, 4 Jun 2009 13:46:41 -0700 Message-Id: <1244148401-12191-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH] target-ppc: fix evmergelo and evmergelohi List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org For 32-bit PPC targets, we translated: evmergelo rX, rX, rY as: rX-lo = rY-lo rX-hi = rX-lo which is wrong, because we should be transferring rX-lo first. This problem is fixed by swapping the order in which we write the parts of rX. Similarly, we translated: evmergelohi rX, rX, rY as: rX-lo = rY-hi rX-hi = rX-lo In this case, we can't swap the assignment statements, because that would just cause problems for: evmergelohi rX, rY, rX Instead, we detect the first case and save rX-lo in a temporary variable: tmp = rX-lo rX-lo = rY-hi rX-hi = tmp These problems don't occur on PPC64 targets because we don't split the SPE registers into hi/lo parts for such targets. Signed-off-by: Nathan Froyd --- target-ppc/translate.c | 14 +++++++++++--- 1 files changed, 11 insertions(+), 3 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 24c78d1..c61667a 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7018,8 +7018,8 @@ static always_inline void gen_evmergelo (DisasContext *ctx) tcg_temp_free(t0); tcg_temp_free(t1); #else - tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); #endif } static always_inline void gen_evmergehilo (DisasContext *ctx) @@ -7056,8 +7056,16 @@ static always_inline void gen_evmergelohi (DisasContext *ctx) tcg_temp_free(t0); tcg_temp_free(t1); #else - tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); - tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + if (rD(ctx->opcode) == rA(ctx->opcode)) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); + tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); + tcg_temp_free_i32(tmp); + } else { + tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); + tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + } #endif } static always_inline void gen_evsplati (DisasContext *ctx) -- 1.6.3.2