From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MCN46-0002nH-3g for qemu-devel@nongnu.org; Thu, 04 Jun 2009 20:13:46 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MCN41-0002l1-2c for qemu-devel@nongnu.org; Thu, 04 Jun 2009 20:13:45 -0400 Received: from [199.232.76.173] (port=52853 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MCMQc-0006Xf-HV for qemu-devel@nongnu.org; Thu, 04 Jun 2009 19:32:58 -0400 Received: from mga02.intel.com ([134.134.136.20]:1888) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MCKWy-0003iY-9H for qemu-devel@nongnu.org; Thu, 04 Jun 2009 17:31:24 -0400 From: Nitin A Kamble Date: Thu, 4 Jun 2009 14:29:50 -0700 Message-Id: <1244150990-8234-1-git-send-email-nitin.a.kamble@intel.com> In-Reply-To: References: Subject: [Qemu-devel] [PATCH] QEMU KVM: i386: Fix the cpu reset state List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: jan.kiszka@siemens.com, avi@redhat.com, kvm@vger.kernel.org, Nitin A Kamble As per the IA32 processor manual, the accessed bit is set to 1 in the processor state after reset. qemu pc cpu_reset code was missing this accessed bit setting. Signed-off-by: Nitin A Kamble --- target-i386/helper.c | 18 ++++++++++++------ 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index 7fc5366..573fb5b 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -493,17 +493,23 @@ void cpu_reset(CPUX86State *env) env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, - DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK); + DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | + DESC_R_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | + DESC_A_MASK); cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | + DESC_A_MASK); cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | + DESC_A_MASK); cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | + DESC_A_MASK); cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | + DESC_A_MASK); env->eip = 0xfff0; env->regs[R_EDX] = env->cpuid_version; -- 1.6.0.6