[Qemu-devel] [PATCH 1/3] lsi53c895a: Implement Scratch Byte Register

[Qemu-devel] [PATCH 1/3] lsi53c895a: Implement Scratch Byte Register

[Sebastian Herbszt]

Fixes the following errors:

lsi_scsi: error: Unhandled writeb 0x3a = 0x0
lsi_scsi: error: readb 0x3a

Signed-off-by: Sebastian Herbszt <herbszt@gmx.de>

Index: qemu-3a2eeac0c9033e30b19d88465c9561f982e9e6d0/hw/lsi53c895a.c
===================================================================
--- qemu-3a2eeac0c9033e30b19d88465c9561f982e9e6d0.orig/hw/lsi53c895a.c
+++ qemu-3a2eeac0c9033e30b19d88465c9561f982e9e6d0/hw/lsi53c895a.c
@@ -262,6 +262,7 @@ typedef struct {
     uint32_t sbc;
     uint32_t csbc;
     uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
+    uint8_t sbr;
 
     /* Script ram is stored as 32-bit words in host byteorder.  */
     uint32_t script_ram[2048];
@@ -330,6 +331,7 @@ static void lsi_soft_reset(LSIState *s)
     s->ia = 0;
     s->sbc = 0;
     s->csbc = 0;
+    s->sbr = 0;
 }
 
 static int lsi_dma_40bit(LSIState *s)
@@ -1408,6 +1410,8 @@ static uint8_t lsi_reg_readb(LSIState *s
         return s->dmode;
     case 0x39: /* DIEN */
         return s->dien;
+    case 0x3a: /* SBR */
+        return s->sbr;
     case 0x3b: /* DCNTL */
         return s->dcntl;
     case 0x40: /* SIEN0 */
@@ -1622,6 +1626,9 @@ static void lsi_reg_writeb(LSIState *s, 
         s->dien = val;
         lsi_update_irq(s);
         break;
+    case 0x3a: /* SBR */
+        s->sbr = val;
+        break;
     case 0x3b: /* DCNTL */
         s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
         if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)

[Qemu-devel] [PATCH 2/3] lsi53c895a: Implement read and write access to DMA Next Address

[Sebastian Herbszt]

Fixes the following errors:

lsi_scsi: error: Unhandled writeb 0x28 = 0x0
lsi_scsi: error: Unhandled writeb 0x29 = 0x0
lsi_scsi: error: Unhandled writeb 0x2a = 0x0
lsi_scsi: error: Unhandled writeb 0x2b = 0x0

Signed-off-by: Sebastian Herbszt <herbszt@gmx.de>

Index: qemu-3a2eeac0c9033e30b19d88465c9561f982e9e6d0/hw/lsi53c895a.c
===================================================================
--- qemu-3a2eeac0c9033e30b19d88465c9561f982e9e6d0.orig/hw/lsi53c895a.c
+++ qemu-3a2eeac0c9033e30b19d88465c9561f982e9e6d0/hw/lsi53c895a.c
@@ -1403,6 +1403,7 @@ static uint8_t lsi_reg_readb(LSIState *s
     CASE_GET_REG24(dbc, 0x24)
     case 0x27: /* DCMD */
         return s->dcmd;
+    CASE_GET_REG32(dnad, 0x28)
     CASE_GET_REG32(dsp, 0x2c)
     CASE_GET_REG32(dsps, 0x30)
     CASE_GET_REG32(scratch[0], 0x34)
@@ -1595,6 +1596,7 @@ static void lsi_reg_writeb(LSIState *s, 
         }
         s->ctest5 = val;
         break;
+    CASE_SET_REG32(dnad, 0x28)
     case 0x2c: /* DSP[0:7] */
         s->dsp &= 0xffffff00;
         s->dsp |= val;

[Qemu-devel] [PATCH 3/3] lsi53c895a: Implement write access to DMA Byte Counter

[Sebastian Herbszt]

Adds CASE_SET_REG24 and fixes the following errors:

lsi_scsi: error: Unhandled writeb 0x24 = 0x0
lsi_scsi: error: Unhandled writeb 0x25 = 0x0

Signed-off-by: Sebastian Herbszt <herbszt@gmx.de>

Index: qemu-1172f6536247c8f5a382e6f9062034b1e9bec631/hw/lsi53c895a.c
===================================================================
--- qemu-1172f6536247c8f5a382e6f9062034b1e9bec631.orig/hw/lsi53c895a.c
+++ qemu-1172f6536247c8f5a382e6f9062034b1e9bec631/hw/lsi53c895a.c
@@ -1492,6 +1492,11 @@ static uint8_t lsi_reg_readb(LSIState *s
 
 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
 {
+#define CASE_SET_REG24(name, addr) \
+    case addr    : s->name &= 0xffffff00; s->name |= val;       break; \
+    case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8;  break; \
+    case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break;
+
 #define CASE_SET_REG32(name, addr) \
     case addr    : s->name &= 0xffffff00; s->name |= val;       break; \
     case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8;  break; \
@@ -1596,6 +1601,7 @@ static void lsi_reg_writeb(LSIState *s, 
         }
         s->ctest5 = val;
         break;
+    CASE_SET_REG24(dbc, 0x24)
     CASE_SET_REG32(dnad, 0x28)
     case 0x2c: /* DSP[0:7] */
         s->dsp &= 0xffffff00;
@@ -1710,6 +1716,7 @@ static void lsi_reg_writeb(LSIState *s, 
             BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
         }
     }
+#undef CASE_SET_REG24
 #undef CASE_SET_REG32
 }