[Qemu-devel] [PATCH 1/3] Minor bugfixes/improvements to arm_gic.

[Logan Gunthorpe <logang@ece.ualberta.ca>]

- Added code to set and clear the Active flags.
- Fixed a bug with the Software Trigger Interrupt register. It was not
  handled correctly in the NVIC version.
---
 hw/arm_gic.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 563397d..4a082c6 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -197,6 +197,8 @@ static uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
     /* Clear pending flags for both level and edge triggered interrupts.
        Level triggered IRQs will be reasserted once they become inactive.  */
     GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm);
+    GIC_SET_ACTIVE(new_irq, cm);
+
     gic_set_running_irq(s, cpu, new_irq);
     DPRINTF("ACK %d\n", new_irq);
     return new_irq;
@@ -209,6 +211,9 @@ static void gic_complete_irq(gic_state * s, int cpu, int irq)
     DPRINTF("EOI %d\n", irq);
     if (s->running_irq[cpu] == 1023)
         return; /* No active IRQ.  */
+
+    GIC_CLEAR_ACTIVE(irq, cm);
+
     if (irq != 1023) {
         /* Mark level triggered interrupts as pending if they are still
            raised.  */
@@ -535,6 +540,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
 
         cpu = gic_get_current_cpu();
         irq = value & 0x3ff;
+
+#ifndef NVIC
         switch ((value >> 24) & 3) {
         case 0:
             mask = (value >> 16) & ALL_CPU_MASK;
@@ -550,6 +557,11 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
             mask = ALL_CPU_MASK;
             break;
         }
+#else
+        mask = ALL_CPU_MASK;
+        irq += GIC_BASE_IRQ;
+#endif
+
         GIC_SET_PENDING(irq, mask);
         gic_update(s);
         return;
-- 
1.5.6.5