[Qemu-devel] [PATCH 0/3] Small patches related to Stelaris/ARMv7 support

[Qemu-devel] [PATCH 0/3] Small patches related to Stelaris/ARMv7 support

[Logan Gunthorpe]

Hi,

I've created three small independent patches to improve the support for
the stelaris microcontroller.

The first patch fixes a couple of minor items in the Arm Interrupt Control$
the second two patches are improvements to the Stelaris peripherals.

Thanks,

Logan


Logan Gunthorpe (3):
  Minor bugfixes/improvements to arm_gic.
  Fixes two bugs with the Stelaris ADC.
  Stelaris 16-bit timer mode.

 hw/arm_gic.c   |   12 ++++++++++++
 hw/stellaris.c |   39 +++++++++++++++++++++++++++------------
 2 files changed, 39 insertions(+), 12 deletions(-)

[Qemu-devel] [PATCH 1/3] Minor bugfixes/improvements to arm_gic.

[Logan Gunthorpe]

- Added code to set and clear the Active flags.
- Fixed a bug with the Software Trigger Interrupt register. It was not
  handled correctly in the NVIC version.
---
 hw/arm_gic.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 563397d..4a082c6 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -197,6 +197,8 @@ static uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
     /* Clear pending flags for both level and edge triggered interrupts.
        Level triggered IRQs will be reasserted once they become inactive.  */
     GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm);
+    GIC_SET_ACTIVE(new_irq, cm);
+
     gic_set_running_irq(s, cpu, new_irq);
     DPRINTF("ACK %d\n", new_irq);
     return new_irq;
@@ -209,6 +211,9 @@ static void gic_complete_irq(gic_state * s, int cpu, int irq)
     DPRINTF("EOI %d\n", irq);
     if (s->running_irq[cpu] == 1023)
         return; /* No active IRQ.  */
+
+    GIC_CLEAR_ACTIVE(irq, cm);
+
     if (irq != 1023) {
         /* Mark level triggered interrupts as pending if they are still
            raised.  */
@@ -535,6 +540,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
 
         cpu = gic_get_current_cpu();
         irq = value & 0x3ff;
+
+#ifndef NVIC
         switch ((value >> 24) & 3) {
         case 0:
             mask = (value >> 16) & ALL_CPU_MASK;
@@ -550,6 +557,11 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
             mask = ALL_CPU_MASK;
             break;
         }
+#else
+        mask = ALL_CPU_MASK;
+        irq += GIC_BASE_IRQ;
+#endif
+
         GIC_SET_PENDING(irq, mask);
         gic_update(s);
         return;
-- 
1.5.6.5

[Qemu-devel] [PATCH 2/3] Fixes two bugs with the Stelaris ADC.

[Logan Gunthorpe]

- The adc gets double-triggered because the stelaris_adc_trigger function
  does not ignore calls when the level is low.
- In the stelaris_adc_fifo_read function there is a slight bug that fails
  to set the empty flag when the tail pointer overflows back to zero.
---
 hw/stellaris.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/hw/stellaris.c b/hw/stellaris.c
index 5f44bff..4fadeec 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -934,7 +934,7 @@ static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
     } else {
         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
-        if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
+        if (((tail + 1) & 0xf) == ((s->fifo[n].state >> 4) & 0xf))
             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
     }
     return s->fifo[n].data[tail];
@@ -976,6 +976,8 @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
     int n;
 
+    if (!level) return;
+
     for (n = 0; n < 4; n++) {
         if ((s->actss & (1 << n)) == 0) {
             continue;
-- 
1.5.6.5

[Qemu-devel] [PATCH 3/3] Stelaris 16-bit timer mode.

[Logan Gunthorpe]

- Finished the 16-bit timer mode in the stelaris module which was previously marked as a TODO.
---
 hw/stellaris.c |   35 ++++++++++++++++++++++++-----------
 1 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/hw/stellaris.c b/hw/stellaris.c
index 4fadeec..f23fb87 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -60,14 +60,16 @@ typedef struct gptm_state {
     QEMUTimer *timer[2];
     /* The timers have an alternate output used to trigger the ADC.  */
     qemu_irq trigger;
-    qemu_irq irq;
+    qemu_irq irq[2];
 } gptm_state;
 
 static void gptm_update_irq(gptm_state *s)
 {
     int level;
-    level = (s->state & s->mask) != 0;
-    qemu_set_irq(s->irq, level);
+    level = ((s->state & s->mask) & 0xf) != 0;
+    qemu_set_irq(s->irq[0], level);
+    level = ((s->state & s->mask) & 0xf00) != 0;
+    qemu_set_irq(s->irq[1], level);
 }
 
 static void gptm_stop(gptm_state *s, int n)
@@ -94,7 +96,7 @@ static void gptm_reload(gptm_state *s, int n, int reset)
     } else if (s->mode[n] == 0xa) {
         /* PWM mode.  Not implemented.  */
     } else {
-        hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
+        tick += (int64_t) s->load[n] * system_clock_scale * (s->prescale[n]+1);
     }
     s->tick[n] = tick;
     qemu_mod_timer(s->timer[n], tick);
@@ -135,7 +137,15 @@ static void gptm_tick(void *opaque)
     } else if (s->mode[n] == 0xa) {
         /* PWM mode.  Not implemented.  */
     } else {
-        hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
+        s->state |= 1 << n*8;
+
+        if (s->mode[n] & 1) {
+            /* One-shot.  */
+            s->control &= ~(1 << n*8);
+        } else {
+            /* Periodic.  */
+            gptm_reload(s, n, 0);
+        }
     }
     gptm_update_irq(s);
 }
@@ -226,11 +236,12 @@ static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value)
         }
         break;
     case 0x18: /* IMR */
-        s->mask = value & 0x77;
+        s->mask = value & 0x0707;
         gptm_update_irq(s);
         break;
     case 0x24: /* CR */
         s->state &= ~value;
+        gptm_update_irq(s);
         break;
     case 0x28: /* TAILR */
         s->load[0] = value & 0xffff;
@@ -265,7 +276,6 @@ static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value)
     default:
         hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
     }
-    gptm_update_irq(s);
 }
 
 static CPUReadMemoryFunc *gptm_readfn[] = {
@@ -344,7 +354,9 @@ static void stellaris_gptm_init(SysBusDevice *dev)
     int iomemtype;
     gptm_state *s = FROM_SYSBUS(gptm_state, dev);
 
-    sysbus_init_irq(dev, &s->irq);
+    sysbus_init_irq(dev, &s->irq[0]);
+    sysbus_init_irq(dev, &s->irq[1]);
+
     qdev_init_gpio_out(&dev->qdev, &s->trigger, 1);
 
     iomemtype = cpu_register_io_memory(gptm_readfn,
@@ -1317,9 +1329,10 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
     }
     for (i = 0; i < 4; i++) {
         if (board->dc2 & (0x10000 << i)) {
-            dev = sysbus_create_simple("stellaris-gptm",
-                                       0x40030000 + i * 0x1000,
-                                       pic[timer_irq[i]]);
+            dev = sysbus_create_varargs("stellaris-gptm",
+                                        0x40030000 + i * 0x1000,
+                                        pic[timer_irq[i]],
+                                        pic[timer_irq[i]+1], NULL);
             /* TODO: This is incorrect, but we get away with it because
                the ADC output is only ever pulsed.  */
             qdev_connect_gpio_out(dev, 0, adc);
-- 
1.5.6.5