[Qemu-devel] RFC: target-arm: vld1.64 and vst1.64 support

[riku.voipio@iki.fi]

From: Riku Voipio <riku.voipio@iki.fi>

The 64bit form of vld1/vst1 was not supported. This has
been tested to be compatible with the memcpy_neon tests
and neon-optimized pixman code.

the current patch doesn't indent the rest of the code
to minimize the patch for RFC purposes. I'd certainly
like a prettier way for this.

Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
---
 target-arm/translate.c |   26 ++++++++++++++++++++++++--
 1 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 4db8d0e..2012c23 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -854,6 +854,12 @@ static inline TCGv gen_ld32(TCGv addr, int index)
     tcg_gen_qemu_ld32u(tmp, addr, index);
     return tmp;
 }
+static inline TCGv_i64 gen_ld64(TCGv addr, int index)
+{
+    TCGv_i64 tmp = tcg_temp_new_i64();
+    tcg_gen_qemu_ld64(tmp, addr, index);
+    return tmp;
+}
 static inline void gen_st8(TCGv val, TCGv addr, int index)
 {
     tcg_gen_qemu_st8(val, addr, index);
@@ -869,6 +875,10 @@ static inline void gen_st32(TCGv val, TCGv addr, int index)
     tcg_gen_qemu_st32(val, addr, index);
     dead_tmp(val);
 }
+static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
+{
+    tcg_gen_qemu_st64(val, addr, index);
+}
 
 static inline void gen_movl_T0_reg(DisasContext *s, int reg)
 {
@@ -3705,7 +3715,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
         /* Load store all elements.  */
         op = (insn >> 8) & 0xf;
         size = (insn >> 6) & 3;
-        if (op > 10 || size == 3)
+        if (op > 10)
             return 1;
         nregs = neon_ls_element_type[op].nregs;
         interleave = neon_ls_element_type[op].interleave;
@@ -3719,6 +3729,18 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
                 gen_movl_T1_reg(s, rn);
                 gen_op_addl_T1_im(1 << size);
             }
+            if (size == 3) {
+                TCGv_i64 tmp64;
+                if (load) {
+                    tmp64 = gen_ld64(cpu_T[1], IS_USER(s));
+                    neon_store_reg64(tmp64, rd);
+                } else { /* bookmark */
+                    tmp64 = tcg_temp_new_i64();
+                    neon_load_reg64(tmp64, rd);
+                    gen_st64(tmp64, cpu_T[1], IS_USER(s));
+                }
+                gen_op_addl_T1_im(stride);
+            } else {
             for (pass = 0; pass < 2; pass++) {
                 if (size == 2) {
                     if (load) {
@@ -3776,7 +3798,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
                         dead_tmp(tmp2);
                     }
                 }
-            }
+            } }
             rd += neon_ls_element_type[op].spacing;
         }
         stride = nregs * 8;
-- 
1.6.2.1