From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MY0dU-0000Rc-Up for qemu-devel@nongnu.org; Mon, 03 Aug 2009 12:43:45 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MY0dP-0000PW-QF for qemu-devel@nongnu.org; Mon, 03 Aug 2009 12:43:44 -0400 Received: from [199.232.76.173] (port=40734 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MY0dP-0000PQ-Ki for qemu-devel@nongnu.org; Mon, 03 Aug 2009 12:43:39 -0400 Received: from mx20.gnu.org ([199.232.41.8]:53122) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MY0dO-0000y1-Oi for qemu-devel@nongnu.org; Mon, 03 Aug 2009 12:43:39 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MY0dI-0007RT-GQ for qemu-devel@nongnu.org; Mon, 03 Aug 2009 12:43:32 -0400 From: Nathan Froyd Date: Mon, 3 Aug 2009 08:43:25 -0700 Message-Id: <1249314209-10230-4-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1249314209-10230-1-git-send-email-froydnj@codesourcery.com> References: <1249314209-10230-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 3/7] target-ppc: retain l{w,d}arx loaded value List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org We do this so we can check on the corresponding stc{w,d}x. whether the value has changed. It's a poor man's form of implementing atomic operations and is valid only for NPTL usermode Linux emulation. Signed-off-by: Nathan Froyd --- target-ppc/cpu.h | 4 +++- target-ppc/helper.c | 2 +- target-ppc/machine.c | 4 ++-- target-ppc/op_helper.c | 4 ++-- target-ppc/translate.c | 13 +++++++++---- 5 files changed, 17 insertions(+), 10 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index fe2257d..7935fcd 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -561,7 +561,9 @@ struct CPUPPCState { /* XER */ target_ulong xer; /* Reservation address */ - target_ulong reserve; + target_ulong reserve_addr; + /* Reservation value */ + target_ulong reserve_val; /* Those ones are used in supervisor mode only */ /* machine state register */ diff --git a/target-ppc/helper.c b/target-ppc/helper.c index b7162df..6eca2e5 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2805,7 +2805,7 @@ void cpu_ppc_reset (void *opaque) env->msr |= (1ULL << MSR_SF); #endif hreg_compute_hflags(env); - env->reserve = (target_ulong)-1ULL; + env->reserve_addr = (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ env->pending_interrupts = 0; env->exception_index = POWERPC_EXCP_NONE; diff --git a/target-ppc/machine.c b/target-ppc/machine.c index 99ba3eb..deb2e2d 100644 --- a/target-ppc/machine.c +++ b/target-ppc/machine.c @@ -20,7 +20,7 @@ void cpu_save(QEMUFile *f, void *opaque) for (i = 0; i < 8; i++) qemu_put_be32s(f, &env->crf[i]); qemu_put_betls(f, &env->xer); - qemu_put_betls(f, &env->reserve); + qemu_put_betls(f, &env->reserve_addr); qemu_put_betls(f, &env->msr); for (i = 0; i < 4; i++) qemu_put_betls(f, &env->tgpr[i]); @@ -107,7 +107,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) for (i = 0; i < 8; i++) qemu_get_be32s(f, &env->crf[i]); qemu_get_betls(f, &env->xer); - qemu_get_betls(f, &env->reserve); + qemu_get_betls(f, &env->reserve_addr); qemu_get_betls(f, &env->msr); for (i = 0; i < 4; i++) qemu_get_betls(f, &env->tgpr[i]); diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c index ad6d8ee..812282c 100644 --- a/target-ppc/op_helper.c +++ b/target-ppc/op_helper.c @@ -329,8 +329,8 @@ static void do_dcbz(target_ulong addr, int dcache_line_size) for (i = 0 ; i < dcache_line_size ; i += 4) { stl(addr + i , 0); } - if (env->reserve == addr) - env->reserve = (target_ulong)-1ULL; + if (env->reserve_addr == addr) + env->reserve_addr = (target_ulong)-1ULL; } void helper_dcbz(target_ulong addr) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 58818c2..06282b6 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -158,7 +158,8 @@ void ppc_translate_init(void) offsetof(CPUState, xer), "xer"); cpu_reserve = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUState, reserve), "reserve"); + offsetof(CPUState, reserve_addr), + "reserve_addr"); cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, fpscr), "fpscr"); @@ -3006,12 +3007,14 @@ static void gen_isync(DisasContext *ctx) static void gen_lwarx(DisasContext *ctx) { TCGv t0; + TCGv gpr = cpu_gpr[rD(ctx->opcode)]; gen_set_access_type(ctx, ACCESS_RES); t0 = tcg_temp_local_new(); gen_addr_reg_index(ctx, t0); gen_check_align(ctx, t0, 0x03); - gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); + gen_qemu_ld32u(ctx, gpr, t0); tcg_gen_mov_tl(cpu_reserve, t0); + tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val)); tcg_temp_free(t0); } @@ -3041,12 +3044,14 @@ static void gen_stwcx_(DisasContext *ctx) static void gen_ldarx(DisasContext *ctx) { TCGv t0; + TCGv gpr = cpu_gpr[rD(ctx->opcode)]; gen_set_access_type(ctx, ACCESS_RES); t0 = tcg_temp_local_new(); gen_addr_reg_index(ctx, t0); gen_check_align(ctx, t0, 0x07); - gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0); + gen_qemu_ld64(ctx, gpr, t0); tcg_gen_mov_tl(cpu_reserve, t0); + tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val)); tcg_temp_free(t0); } @@ -8834,7 +8839,7 @@ void cpu_dump_state (CPUState *env, FILE *f, a = 'E'; cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); } - cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve); + cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve_addr); for (i = 0; i < 32; i++) { if ((i & (RFPL - 1)) == 0) cpu_fprintf(f, "FPR%02d", i); -- 1.6.3.2