From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Brian Cain <brian.cain@oss.qualcomm.com>, qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org,
matheus.bernardino@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng,
marco.liebel@oss.qualcomm.com, ltaylorsimpson@gmail.com,
alex.bennee@linaro.org, quic_mburton@quicinc.com,
sid.manning@oss.qualcomm.com
Subject: Re: [PATCH v2 02/11] hw/hexagon: Add global register tracing
Date: Thu, 2 Oct 2025 07:42:48 +0200 [thread overview]
Message-ID: <124c48b0-eea0-413f-a1dc-1ede32a7092c@linaro.org> (raw)
In-Reply-To: <20250902034951.1948194-3-brian.cain@oss.qualcomm.com>
On 2/9/25 05:49, Brian Cain wrote:
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
> meson.build | 1 +
> hw/hexagon/hexagon_globalreg.c | 73 ++++++++++++++++++++++++++++++++++
> hw/hexagon/trace-events | 3 ++
> 3 files changed, 77 insertions(+)
> create mode 100644 hw/hexagon/trace-events
> @@ -99,6 +171,7 @@ void hexagon_globalreg_write(HexagonCPU *cpu, uint32_t reg,
> g_assert(reg < NUM_SREGS);
> g_assert(reg >= HEX_SREG_GLB_START);
> s->regs[reg] = value;
> + trace_hexagon_globalreg_write(get_sreg_name(reg), value);
> }
>
> uint32_t hexagon_globalreg_masked_value(HexagonCPU *cpu, uint32_t reg,
> diff --git a/hw/hexagon/trace-events b/hw/hexagon/trace-events
> new file mode 100644
> index 0000000000..6ef88d9e05
> --- /dev/null
> +++ b/hw/hexagon/trace-events
> @@ -0,0 +1,3 @@
> +# Hexagon global register access
> +hexagon_globalreg_read(const char *reg_name, uint32_t value) "reg=%s value=0x%x"
> +hexagon_globalreg_write(const char *reg_name, uint32_t value) "reg=%s value=0x%x"
Maybe worth also tracing the cpuid, regardless:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2025-10-02 5:46 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-02 3:49 [PATCH v2 00/11] hexagon system emulation v2, part 3/3 Brian Cain
2025-09-02 3:49 ` [PATCH v2 01/11] hw/hexagon: Add globalreg model Brian Cain
2025-09-02 3:49 ` [PATCH v2 02/11] hw/hexagon: Add global register tracing Brian Cain
2025-10-02 5:42 ` Philippe Mathieu-Daudé [this message]
2025-09-02 3:49 ` [PATCH v2 03/11] hw/hexagon: Add machine configs for sysemu Brian Cain
2025-09-02 3:49 ` [PATCH v2 04/11] hw/hexagon: Add v68, sa8775-cdsp0 defs Brian Cain
2025-09-02 3:49 ` [PATCH v2 05/11] hw/hexagon: Add support for cfgbase Brian Cain
2025-09-02 3:49 ` [PATCH v2 06/11] hw/hexagon: Modify "Standalone" symbols Brian Cain
2025-09-02 3:49 ` [PATCH v2 07/11] target/hexagon: add build config for softmmu Brian Cain
2025-09-02 3:49 ` [PATCH v2 08/11] hw/hexagon: Define hexagon "virt" machine Brian Cain
2025-09-02 3:49 ` [PATCH v2 09/11] tests/qtest: Add hexagon boot-serial-test Brian Cain
2025-09-02 3:49 ` [PATCH v2 10/11] hw/timer: Add QTimer device Brian Cain
2025-09-02 3:49 ` [PATCH v2 11/11] hw/intc: Add l2vic interrupt controller Brian Cain
2025-09-02 8:11 ` [PATCH v2 00/11] hexagon system emulation v2, part 3/3 Philippe Mathieu-Daudé
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