* [Qemu-devel] [PATCH 1/8] ide: add IDEBus struct, cleanups
2009-08-18 16:06 [Qemu-devel] [PATCH 0/8] ide: cleanup and splitting Gerd Hoffmann
@ 2009-08-18 16:06 ` Gerd Hoffmann
2009-08-19 9:49 ` [Qemu-devel] " Juan Quintela
2009-08-18 16:06 ` [Qemu-devel] [PATCH 2/8] ide: split away ide-isa.c Gerd Hoffmann
` (7 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Gerd Hoffmann @ 2009-08-18 16:06 UTC (permalink / raw)
To: qemu-devel; +Cc: Gerd Hoffmann
The current IDE code uses an array of two IDEState structs to maintain
the IDE bus. This patch adds a IDEBus to be used instead and does a
bunch of cleanups:
* move ide bus state from IDEState to IDEBus.
* drop a bunch of ugly pointer arithmetics to figure the active
interface, explicitly save the interface number instead.
* add helper functions to save/restore idebus state.
It also fixes a save/restore bug: loadvm allways stores the command in
the master's IDEState, even when it was saved from the slave.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
hw/ide.c | 471 ++++++++++++++++++++++++++++++++------------------------------
1 files changed, 245 insertions(+), 226 deletions(-)
diff --git a/hw/ide.c b/hw/ide.c
index 1e38ae3..f5803f1 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -35,6 +35,11 @@
#include "mac_dbdma.h"
#include "sh.h"
#include "dma.h"
+#include "ide.h"
+
+typedef struct IDEBus IDEBus;
+typedef struct IDEState IDEState;
+typedef struct BMDMAState BMDMAState;
/* debug IDE devices */
//#define DEBUG_IDE
@@ -372,12 +377,12 @@
#define SENSE_ILLEGAL_REQUEST 5
#define SENSE_UNIT_ATTENTION 6
-struct IDEState;
-
-typedef void EndTransferFunc(struct IDEState *);
+typedef void EndTransferFunc(IDEState *);
/* NOTE: IDEState represents in fact one drive */
-typedef struct IDEState {
+struct IDEState {
+ IDEBus *bus;
+ uint8_t unit;
/* ide config */
int is_cdrom;
int is_cf;
@@ -387,8 +392,6 @@ typedef struct IDEState {
int identify_set;
uint16_t identify_data[256];
qemu_irq irq;
- PCIDevice *pci_dev;
- struct BMDMAState *bmdma;
int drive_serial;
char drive_serial_str[21];
/* ide regs */
@@ -412,8 +415,6 @@ typedef struct IDEState {
uint8_t cmd;
/* set for lba48 access */
uint8_t lba48;
- /* depends on bit 4 in select, only meaningful for drive 0 */
- struct IDEState *cur_drive;
BlockDriverState *bs;
/* ATAPI specific */
uint8_t sense_key;
@@ -444,7 +445,14 @@ typedef struct IDEState {
int media_changed;
/* for pmac */
int is_read;
-} IDEState;
+};
+
+struct IDEBus {
+ BusState qbus;
+ BMDMAState *bmdma;
+ IDEState ifs[2];
+ uint8_t unit;
+};
/* XXX: DVDs that could fit on a CD will be reported as a CD */
static inline int media_present(IDEState *s)
@@ -484,18 +492,19 @@ static inline int media_is_cd(IDEState *s)
#define UDIDETCR0 0x73
#define UDIDETCR1 0x7B
-typedef struct BMDMAState {
+struct BMDMAState {
uint8_t cmd;
uint8_t status;
uint32_t addr;
struct PCIIDEState *pci_dev;
+ IDEBus *bus;
/* current transfer state */
uint32_t cur_addr;
uint32_t cur_prd_last;
uint32_t cur_prd_addr;
uint32_t cur_prd_len;
- IDEState *ide_if;
+ uint8_t unit;
BlockDriverCompletionFunc *dma_cb;
BlockDriverAIOCB *aiocb;
struct iovec iov;
@@ -503,15 +512,26 @@ typedef struct BMDMAState {
int64_t sector_num;
uint32_t nsector;
QEMUBH *bh;
-} BMDMAState;
+};
typedef struct PCIIDEState {
PCIDevice dev;
- IDEState ide_if[4];
+ IDEBus bus[2];
BMDMAState bmdma[2];
int type; /* see IDE_TYPE_xxx */
} PCIIDEState;
+static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
+{
+ assert(bmdma->unit != -1);
+ return bmdma->bus->ifs + bmdma->unit;
+}
+
+static inline IDEState *idebus_active_if(IDEBus *bus)
+{
+ return bus->ifs + bus->unit;
+}
+
static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb);
static void ide_dma_restart(IDEState *s);
static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret);
@@ -761,7 +781,7 @@ static inline void ide_dma_submit_check(IDEState *s,
static inline void ide_set_irq(IDEState *s)
{
- BMDMAState *bm = s->bmdma;
+ BMDMAState *bm = s->bus->bmdma;
if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
if (bm) {
bm->status |= BM_STATUS_INT;
@@ -877,7 +897,7 @@ static void ide_sector_read(IDEState *s)
/* return 0 if buffer completed */
static int dma_buf_prepare(BMDMAState *bm, int is_write)
{
- IDEState *s = bm->ide_if;
+ IDEState *s = bmdma_active_if(bm);
struct {
uint32_t addr;
uint32_t size;
@@ -936,8 +956,8 @@ static int ide_handle_write_error(IDEState *s, int error, int op)
if ((error == ENOSPC && action == BLOCK_ERR_STOP_ENOSPC)
|| action == BLOCK_ERR_STOP_ANY) {
- s->bmdma->ide_if = s;
- s->bmdma->status |= op;
+ s->bus->bmdma->unit = s->unit;
+ s->bus->bmdma->status |= op;
vm_stop(0);
} else {
if (op == BM_STATUS_DMA_RETRY) {
@@ -954,7 +974,7 @@ static int ide_handle_write_error(IDEState *s, int error, int op)
/* return 0 if buffer completed */
static int dma_buf_rw(BMDMAState *bm, int is_write)
{
- IDEState *s = bm->ide_if;
+ IDEState *s = bmdma_active_if(bm);
struct {
uint32_t addr;
uint32_t size;
@@ -1002,7 +1022,7 @@ static int dma_buf_rw(BMDMAState *bm, int is_write)
static void ide_read_dma_cb(void *opaque, int ret)
{
BMDMAState *bm = opaque;
- IDEState *s = bm->ide_if;
+ IDEState *s = bmdma_active_if(bm);
int n;
int64_t sector_num;
@@ -1029,7 +1049,7 @@ static void ide_read_dma_cb(void *opaque, int ret)
bm->status &= ~BM_STATUS_DMAING;
bm->status |= BM_STATUS_INT;
bm->dma_cb = NULL;
- bm->ide_if = NULL;
+ bm->unit = -1;
bm->aiocb = NULL;
return;
}
@@ -1120,10 +1140,10 @@ static void ide_dma_restart_bh(void *opaque)
if (bm->status & BM_STATUS_DMA_RETRY) {
bm->status &= ~BM_STATUS_DMA_RETRY;
- ide_dma_restart(bm->ide_if);
+ ide_dma_restart(bmdma_active_if(bm));
} else if (bm->status & BM_STATUS_PIO_RETRY) {
bm->status &= ~BM_STATUS_PIO_RETRY;
- ide_sector_write(bm->ide_if);
+ ide_sector_write(bmdma_active_if(bm));
}
}
@@ -1143,7 +1163,7 @@ static void ide_dma_restart_cb(void *opaque, int running, int reason)
static void ide_write_dma_cb(void *opaque, int ret)
{
BMDMAState *bm = opaque;
- IDEState *s = bm->ide_if;
+ IDEState *s = bmdma_active_if(bm);
int n;
int64_t sector_num;
@@ -1169,7 +1189,7 @@ static void ide_write_dma_cb(void *opaque, int ret)
bm->status &= ~BM_STATUS_DMAING;
bm->status |= BM_STATUS_INT;
bm->dma_cb = NULL;
- bm->ide_if = NULL;
+ bm->unit = -1;
bm->aiocb = NULL;
return;
}
@@ -1429,7 +1449,7 @@ static void ide_atapi_cmd_read_pio(IDEState *s, int lba, int nb_sectors,
static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret)
{
BMDMAState *bm = opaque;
- IDEState *s = bm->ide_if;
+ IDEState *s = bmdma_active_if(bm);
int data_offset, n;
if (ret < 0) {
@@ -1467,7 +1487,7 @@ static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret)
bm->status &= ~BM_STATUS_DMAING;
bm->status |= BM_STATUS_INT;
bm->dma_cb = NULL;
- bm->ide_if = NULL;
+ bm->unit = -1;
bm->aiocb = NULL;
return;
}
@@ -2151,18 +2171,18 @@ static void ide_cmd_lba48_transform(IDEState *s, int lba48)
}
}
-static void ide_clear_hob(IDEState *ide_if)
+static void ide_clear_hob(IDEBus *bus)
{
/* any write clears HOB high bit of device control register */
- ide_if[0].select &= ~(1 << 7);
- ide_if[1].select &= ~(1 << 7);
+ bus->ifs[0].select &= ~(1 << 7);
+ bus->ifs[1].select &= ~(1 << 7);
}
static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
- IDEState *ide_if = opaque;
+ IDEBus *bus = opaque;
IDEState *s;
- int unit, n;
+ int n;
int lba48 = 0;
#ifdef DEBUG_IDE
@@ -2172,56 +2192,54 @@ static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
addr &= 7;
/* ignore writes to command block while busy with previous command */
- if (addr != 7 && (ide_if->cur_drive->status & (BUSY_STAT|DRQ_STAT)))
+ if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
return;
switch(addr) {
case 0:
break;
case 1:
- ide_clear_hob(ide_if);
+ ide_clear_hob(bus);
/* NOTE: data is written to the two drives */
- ide_if[0].hob_feature = ide_if[0].feature;
- ide_if[1].hob_feature = ide_if[1].feature;
- ide_if[0].feature = val;
- ide_if[1].feature = val;
+ bus->ifs[0].hob_feature = bus->ifs[0].feature;
+ bus->ifs[1].hob_feature = bus->ifs[1].feature;
+ bus->ifs[0].feature = val;
+ bus->ifs[1].feature = val;
break;
case 2:
- ide_clear_hob(ide_if);
- ide_if[0].hob_nsector = ide_if[0].nsector;
- ide_if[1].hob_nsector = ide_if[1].nsector;
- ide_if[0].nsector = val;
- ide_if[1].nsector = val;
+ ide_clear_hob(bus);
+ bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
+ bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
+ bus->ifs[0].nsector = val;
+ bus->ifs[1].nsector = val;
break;
case 3:
- ide_clear_hob(ide_if);
- ide_if[0].hob_sector = ide_if[0].sector;
- ide_if[1].hob_sector = ide_if[1].sector;
- ide_if[0].sector = val;
- ide_if[1].sector = val;
+ ide_clear_hob(bus);
+ bus->ifs[0].hob_sector = bus->ifs[0].sector;
+ bus->ifs[1].hob_sector = bus->ifs[1].sector;
+ bus->ifs[0].sector = val;
+ bus->ifs[1].sector = val;
break;
case 4:
- ide_clear_hob(ide_if);
- ide_if[0].hob_lcyl = ide_if[0].lcyl;
- ide_if[1].hob_lcyl = ide_if[1].lcyl;
- ide_if[0].lcyl = val;
- ide_if[1].lcyl = val;
+ ide_clear_hob(bus);
+ bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
+ bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
+ bus->ifs[0].lcyl = val;
+ bus->ifs[1].lcyl = val;
break;
case 5:
- ide_clear_hob(ide_if);
- ide_if[0].hob_hcyl = ide_if[0].hcyl;
- ide_if[1].hob_hcyl = ide_if[1].hcyl;
- ide_if[0].hcyl = val;
- ide_if[1].hcyl = val;
+ ide_clear_hob(bus);
+ bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
+ bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
+ bus->ifs[0].hcyl = val;
+ bus->ifs[1].hcyl = val;
break;
case 6:
/* FIXME: HOB readback uses bit 7 */
- ide_if[0].select = (val & ~0x10) | 0xa0;
- ide_if[1].select = (val | 0x10) | 0xa0;
+ bus->ifs[0].select = (val & ~0x10) | 0xa0;
+ bus->ifs[1].select = (val | 0x10) | 0xa0;
/* select drive */
- unit = (val >> 4) & 1;
- s = ide_if + unit;
- ide_if->cur_drive = s;
+ bus->unit = (val >> 4) & 1;
break;
default:
case 7:
@@ -2229,9 +2247,9 @@ static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
#if defined(DEBUG_IDE)
printf("ide: CMD=%02x\n", val);
#endif
- s = ide_if->cur_drive;
+ s = idebus_active_if(bus);
/* ignore commands to non existant slave */
- if (s != ide_if && !s->bs)
+ if (s != bus->ifs && !s->bs)
break;
/* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
@@ -2578,8 +2596,8 @@ static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
{
- IDEState *ide_if = opaque;
- IDEState *s = ide_if->cur_drive;
+ IDEBus *bus = opaque;
+ IDEState *s = idebus_active_if(bus);
uint32_t addr;
int ret, hob;
@@ -2592,8 +2610,8 @@ static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
ret = 0xff;
break;
case 1:
- if ((!ide_if[0].bs && !ide_if[1].bs) ||
- (s != ide_if && !s->bs))
+ if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
+ (s != bus->ifs && !s->bs))
ret = 0;
else if (!hob)
ret = s->error;
@@ -2601,7 +2619,7 @@ static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
ret = s->hob_feature;
break;
case 2:
- if (!ide_if[0].bs && !ide_if[1].bs)
+ if (!bus->ifs[0].bs && !bus->ifs[1].bs)
ret = 0;
else if (!hob)
ret = s->nsector & 0xff;
@@ -2609,7 +2627,7 @@ static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
ret = s->hob_nsector;
break;
case 3:
- if (!ide_if[0].bs && !ide_if[1].bs)
+ if (!bus->ifs[0].bs && !bus->ifs[1].bs)
ret = 0;
else if (!hob)
ret = s->sector;
@@ -2617,7 +2635,7 @@ static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
ret = s->hob_sector;
break;
case 4:
- if (!ide_if[0].bs && !ide_if[1].bs)
+ if (!bus->ifs[0].bs && !bus->ifs[1].bs)
ret = 0;
else if (!hob)
ret = s->lcyl;
@@ -2625,7 +2643,7 @@ static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
ret = s->hob_lcyl;
break;
case 5:
- if (!ide_if[0].bs && !ide_if[1].bs)
+ if (!bus->ifs[0].bs && !bus->ifs[1].bs)
ret = 0;
else if (!hob)
ret = s->hcyl;
@@ -2633,15 +2651,15 @@ static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
ret = s->hob_hcyl;
break;
case 6:
- if (!ide_if[0].bs && !ide_if[1].bs)
+ if (!bus->ifs[0].bs && !bus->ifs[1].bs)
ret = 0;
else
ret = s->select;
break;
default:
case 7:
- if ((!ide_if[0].bs && !ide_if[1].bs) ||
- (s != ide_if && !s->bs))
+ if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
+ (s != bus->ifs && !s->bs))
ret = 0;
else
ret = s->status;
@@ -2656,12 +2674,12 @@ static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
static uint32_t ide_status_read(void *opaque, uint32_t addr)
{
- IDEState *ide_if = opaque;
- IDEState *s = ide_if->cur_drive;
+ IDEBus *bus = opaque;
+ IDEState *s = idebus_active_if(bus);
int ret;
- if ((!ide_if[0].bs && !ide_if[1].bs) ||
- (s != ide_if && !s->bs))
+ if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
+ (s != bus->ifs && !s->bs))
ret = 0;
else
ret = s->status;
@@ -2673,7 +2691,7 @@ static uint32_t ide_status_read(void *opaque, uint32_t addr)
static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
{
- IDEState *ide_if = opaque;
+ IDEBus *bus = opaque;
IDEState *s;
int i;
@@ -2681,19 +2699,19 @@ static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
printf("ide: write control addr=0x%x val=%02x\n", addr, val);
#endif
/* common for both drives */
- if (!(ide_if[0].cmd & IDE_CMD_RESET) &&
+ if (!(bus->ifs[0].cmd & IDE_CMD_RESET) &&
(val & IDE_CMD_RESET)) {
/* reset low to high */
for(i = 0;i < 2; i++) {
- s = &ide_if[i];
+ s = &bus->ifs[i];
s->status = BUSY_STAT | SEEK_STAT;
s->error = 0x01;
}
- } else if ((ide_if[0].cmd & IDE_CMD_RESET) &&
+ } else if ((bus->ifs[0].cmd & IDE_CMD_RESET) &&
!(val & IDE_CMD_RESET)) {
/* high to low */
for(i = 0;i < 2; i++) {
- s = &ide_if[i];
+ s = &bus->ifs[i];
if (s->is_cdrom)
s->status = 0x00; /* NOTE: READY is _not_ set */
else
@@ -2702,13 +2720,14 @@ static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
}
}
- ide_if[0].cmd = val;
- ide_if[1].cmd = val;
+ bus->ifs[0].cmd = val;
+ bus->ifs[1].cmd = val;
}
static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
{
- IDEState *s = ((IDEState *)opaque)->cur_drive;
+ IDEBus *bus = opaque;
+ IDEState *s = idebus_active_if(bus);
uint8_t *p;
/* PIO data access allowed only when DRQ bit is set */
@@ -2725,7 +2744,8 @@ static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
static uint32_t ide_data_readw(void *opaque, uint32_t addr)
{
- IDEState *s = ((IDEState *)opaque)->cur_drive;
+ IDEBus *bus = opaque;
+ IDEState *s = idebus_active_if(bus);
uint8_t *p;
int ret;
@@ -2744,7 +2764,8 @@ static uint32_t ide_data_readw(void *opaque, uint32_t addr)
static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
{
- IDEState *s = ((IDEState *)opaque)->cur_drive;
+ IDEBus *bus = opaque;
+ IDEState *s = idebus_active_if(bus);
uint8_t *p;
/* PIO data access allowed only when DRQ bit is set */
@@ -2761,7 +2782,8 @@ static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
static uint32_t ide_data_readl(void *opaque, uint32_t addr)
{
- IDEState *s = ((IDEState *)opaque)->cur_drive;
+ IDEBus *bus = opaque;
+ IDEState *s = idebus_active_if(bus);
uint8_t *p;
int ret;
@@ -2790,11 +2812,13 @@ static void ide_dummy_transfer_stop(IDEState *s)
static void ide_reset(IDEState *s)
{
+ IDEBus *bus = s->bus;
+
if (s->is_cf)
s->mult_sectors = 0;
else
s->mult_sectors = MAX_MULT_SECTORS;
- s->cur_drive = s;
+ bus->unit = s->unit;
s->select = 0xa0;
s->status = READY_STAT | SEEK_STAT;
ide_set_signature(s);
@@ -2805,7 +2829,7 @@ static void ide_reset(IDEState *s)
s->media_changed = 0;
}
-static void ide_init2(IDEState *ide_state,
+static void ide_init2(IDEBus *bus,
BlockDriverState *hd0, BlockDriverState *hd1,
qemu_irq irq)
{
@@ -2815,11 +2839,10 @@ static void ide_init2(IDEState *ide_state,
uint64_t nb_sectors;
for(i = 0; i < 2; i++) {
- s = ide_state + i;
- if (i == 0)
- s->bs = hd0;
- else
- s->bs = hd1;
+ s = bus->ifs + i;
+ s->bus = bus;
+ s->unit = i;
+ s->bs = (i == 0) ? hd0 : hd1;
s->io_buffer = qemu_blockalign(s->bs, IDE_DMA_BUF_SECTORS*512 + 4);
if (s->bs) {
bdrv_get_geometry(s->bs, &nb_sectors);
@@ -2847,20 +2870,20 @@ static void ide_init2(IDEState *ide_state,
}
}
-static void ide_init_ioport(IDEState *ide_state, int iobase, int iobase2)
+static void ide_init_ioport(IDEBus *bus, int iobase, int iobase2)
{
- register_ioport_write(iobase, 8, 1, ide_ioport_write, ide_state);
- register_ioport_read(iobase, 8, 1, ide_ioport_read, ide_state);
+ register_ioport_write(iobase, 8, 1, ide_ioport_write, bus);
+ register_ioport_read(iobase, 8, 1, ide_ioport_read, bus);
if (iobase2) {
- register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state);
- register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state);
+ register_ioport_read(iobase2, 1, 1, ide_status_read, bus);
+ register_ioport_write(iobase2, 1, 1, ide_cmd_write, bus);
}
/* data ports */
- register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state);
- register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state);
- register_ioport_write(iobase, 4, 4, ide_data_writel, ide_state);
- register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state);
+ register_ioport_write(iobase, 2, 2, ide_data_writew, bus);
+ register_ioport_read(iobase, 2, 2, ide_data_readw, bus);
+ register_ioport_write(iobase, 4, 4, ide_data_writel, bus);
+ register_ioport_read(iobase, 4, 4, ide_data_readl, bus);
}
/* save per IDE drive data */
@@ -2927,18 +2950,36 @@ static void ide_load(QEMUFile* f, IDEState *s, int version_id)
/* XXX: if a transfer is pending, we do not save it yet */
}
+static void idebus_save(QEMUFile* f, IDEBus *bus)
+{
+ IDEState *s = idebus_active_if(bus);
+ qemu_put_8s(f, &s->cmd);
+ qemu_put_8s(f, &bus->unit);
+}
+
+static void idebus_load(QEMUFile* f, IDEBus *bus, int version_id)
+{
+ IDEState *s;
+ uint8_t cmd;
+
+ qemu_get_8s(f, &cmd);
+ qemu_get_8s(f, &bus->unit);
+ s = idebus_active_if(bus);
+ s->cmd = cmd;
+}
+
/***********************************************************/
/* ISA IDE definitions */
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
BlockDriverState *hd0, BlockDriverState *hd1)
{
- IDEState *ide_state;
+ IDEBus *bus;
- ide_state = qemu_mallocz(sizeof(IDEState) * 2);
+ bus = qemu_mallocz(sizeof(*bus));
- ide_init2(ide_state, hd0, hd1, irq);
- ide_init_ioport(ide_state, iobase, iobase2);
+ ide_init2(bus, hd0, hd1, irq);
+ ide_init_ioport(bus, iobase, iobase2);
}
/***********************************************************/
@@ -2950,32 +2991,32 @@ static void ide_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
PCIIDEState *d = (PCIIDEState *)pci_dev;
- IDEState *ide_state;
+ IDEBus *bus;
if (region_num <= 3) {
- ide_state = &d->ide_if[(region_num >> 1) * 2];
+ bus = &d->bus[(region_num >> 1)];
if (region_num & 1) {
- register_ioport_read(addr + 2, 1, 1, ide_status_read, ide_state);
- register_ioport_write(addr + 2, 1, 1, ide_cmd_write, ide_state);
+ register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
+ register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
} else {
- register_ioport_write(addr, 8, 1, ide_ioport_write, ide_state);
- register_ioport_read(addr, 8, 1, ide_ioport_read, ide_state);
+ register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
+ register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
/* data ports */
- register_ioport_write(addr, 2, 2, ide_data_writew, ide_state);
- register_ioport_read(addr, 2, 2, ide_data_readw, ide_state);
- register_ioport_write(addr, 4, 4, ide_data_writel, ide_state);
- register_ioport_read(addr, 4, 4, ide_data_readl, ide_state);
+ register_ioport_write(addr, 2, 2, ide_data_writew, bus);
+ register_ioport_read(addr, 2, 2, ide_data_readw, bus);
+ register_ioport_write(addr, 4, 4, ide_data_writel, bus);
+ register_ioport_read(addr, 4, 4, ide_data_readl, bus);
}
}
}
static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb)
{
- BMDMAState *bm = s->bmdma;
+ BMDMAState *bm = s->bus->bmdma;
if(!bm)
return;
- bm->ide_if = s;
+ bm->unit = s->unit;
bm->dma_cb = dma_cb;
bm->cur_prd_last = 0;
bm->cur_prd_addr = 0;
@@ -2989,7 +3030,7 @@ static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb)
static void ide_dma_restart(IDEState *s)
{
- BMDMAState *bm = s->bmdma;
+ BMDMAState *bm = s->bus->bmdma;
ide_set_sector(s, bm->sector_num);
s->io_buffer_index = 0;
s->io_buffer_size = 0;
@@ -3004,7 +3045,7 @@ static void ide_dma_cancel(BMDMAState *bm)
if (bm->status & BM_STATUS_DMAING) {
bm->status &= ~BM_STATUS_DMAING;
/* cancel DMA request */
- bm->ide_if = NULL;
+ bm->unit = -1;
bm->dma_cb = NULL;
if (bm->aiocb) {
#ifdef DEBUG_AIO
@@ -3185,9 +3226,9 @@ static void bmdma_map(PCIDevice *pci_dev, int region_num,
for(i = 0;i < 2; i++) {
BMDMAState *bm = &d->bmdma[i];
- d->ide_if[2 * i].bmdma = bm;
- d->ide_if[2 * i + 1].bmdma = bm;
- bm->pci_dev = (PCIIDEState *)pci_dev;
+ d->bus[i].bmdma = bm;
+ bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev);
+ bm->bus = d->bus+i;
qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
@@ -3220,23 +3261,20 @@ static void pci_ide_save(QEMUFile* f, void *opaque)
qemu_put_be32s(f, &bm->addr);
qemu_put_sbe64s(f, &bm->sector_num);
qemu_put_be32s(f, &bm->nsector);
- ifidx = bm->ide_if ? bm->ide_if - d->ide_if : 0;
+ ifidx = bm->unit + 2*i;
qemu_put_8s(f, &ifidx);
/* XXX: if a transfer is pending, we do not save it yet */
}
/* per IDE interface data */
for(i = 0; i < 2; i++) {
- IDEState *s = &d->ide_if[i * 2];
- uint8_t drive1_selected;
- qemu_put_8s(f, &s->cmd);
- drive1_selected = (s->cur_drive != s);
- qemu_put_8s(f, &drive1_selected);
+ idebus_save(f, &d->bus[i]);
}
/* per IDE drive data */
- for(i = 0; i < 4; i++) {
- ide_save(f, &d->ide_if[i]);
+ for(i = 0; i < 2; i++) {
+ ide_save(f, &d->bus[i].ifs[0]);
+ ide_save(f, &d->bus[i].ifs[1]);
}
}
@@ -3260,22 +3298,19 @@ static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_sbe64s(f, &bm->sector_num);
qemu_get_be32s(f, &bm->nsector);
qemu_get_8s(f, &ifidx);
- bm->ide_if = &d->ide_if[ifidx];
+ bm->unit = ifidx & 1;
/* XXX: if a transfer is pending, we do not save it yet */
}
/* per IDE interface data */
for(i = 0; i < 2; i++) {
- IDEState *s = &d->ide_if[i * 2];
- uint8_t drive1_selected;
- qemu_get_8s(f, &s->cmd);
- qemu_get_8s(f, &drive1_selected);
- s->cur_drive = &d->ide_if[i * 2 + (drive1_selected != 0)];
+ idebus_load(f, &d->bus[i], version_id);
}
/* per IDE drive data */
- for(i = 0; i < 4; i++) {
- ide_load(f, &d->ide_if[i], version_id);
+ for(i = 0; i < 2; i++) {
+ ide_load(f, &d->bus[i].ifs[0], version_id);
+ ide_load(f, &d->bus[i].ifs[1], version_id);
}
return 0;
}
@@ -3321,7 +3356,6 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
{
PCIIDEState *d;
uint8_t *pci_conf;
- int i;
qemu_irq *irq;
d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
@@ -3358,12 +3392,9 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
pci_conf[0x3d] = 0x01; // interrupt on pin 1
- for(i = 0; i < 4; i++)
- d->ide_if[i].pci_dev = (PCIDevice *)d;
-
irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
- ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], irq[0]);
- ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);
+ ide_init2(&d->bus[0], hd_table[0], hd_table[1], irq[0]);
+ ide_init2(&d->bus[1], hd_table[2], hd_table[3], irq[1]);
register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
qemu_register_reset(cmd646_reset, d);
@@ -3415,10 +3446,10 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
pci_register_bar((PCIDevice *)d, 4, 0x10,
PCI_ADDRESS_SPACE_IO, bmdma_map);
- ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
- ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]);
- ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
- ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
+ ide_init2(&d->bus[0], hd_table[0], hd_table[1], pic[14]);
+ ide_init2(&d->bus[1], hd_table[2], hd_table[3], pic[15]);
+ ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
+ ide_init_ioport(&d->bus[1], 0x170, 0x376);
for (i = 0; i < 4; i++)
if (hd_table[i])
@@ -3455,10 +3486,10 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
pci_register_bar((PCIDevice *)d, 4, 0x10,
PCI_ADDRESS_SPACE_IO, bmdma_map);
- ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
- ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]);
- ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
- ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
+ ide_init2(&d->bus[0], hd_table[0], hd_table[1], pic[14]);
+ ide_init2(&d->bus[1], hd_table[2], hd_table[3], pic[15]);
+ ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
+ ide_init_ioport(&d->bus[1], 0x170, 0x376);
register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
}
@@ -3468,7 +3499,7 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
/* MacIO based PowerPC IDE */
typedef struct MACIOIDEState {
- IDEState ide_if[2];
+ IDEBus bus;
BlockDriverAIOCB *aiocb;
} MACIOIDEState;
@@ -3476,7 +3507,7 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
{
DBDMA_io *io = opaque;
MACIOIDEState *m = io->opaque;
- IDEState *s = m->ide_if->cur_drive;
+ IDEState *s = idebus_active_if(&m->bus);
if (ret < 0) {
m->aiocb = NULL;
@@ -3531,7 +3562,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
{
DBDMA_io *io = opaque;
MACIOIDEState *m = io->opaque;
- IDEState *s = m->ide_if->cur_drive;
+ IDEState *s = idebus_active_if(&m->bus);
int n;
int64_t sector_num;
@@ -3589,7 +3620,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
static void pmac_ide_transfer(DBDMA_io *io)
{
MACIOIDEState *m = io->opaque;
- IDEState *s = m->ide_if->cur_drive;
+ IDEState *s = idebus_active_if(&m->bus);
s->io_buffer_size = 0;
if (s->is_cdrom) {
@@ -3617,11 +3648,11 @@ static void pmac_ide_writeb (void *opaque,
addr = (addr & 0xFFF) >> 4;
switch (addr) {
case 1 ... 7:
- ide_ioport_write(d->ide_if, addr, val);
+ ide_ioport_write(&d->bus, addr, val);
break;
case 8:
case 22:
- ide_cmd_write(d->ide_if, 0, val);
+ ide_cmd_write(&d->bus, 0, val);
break;
default:
break;
@@ -3636,11 +3667,11 @@ static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
addr = (addr & 0xFFF) >> 4;
switch (addr) {
case 1 ... 7:
- retval = ide_ioport_read(d->ide_if, addr);
+ retval = ide_ioport_read(&d->bus, addr);
break;
case 8:
case 22:
- retval = ide_status_read(d->ide_if, 0);
+ retval = ide_status_read(&d->bus, 0);
break;
default:
retval = 0xFF;
@@ -3659,7 +3690,7 @@ static void pmac_ide_writew (void *opaque,
val = bswap16(val);
#endif
if (addr == 0) {
- ide_data_writew(d->ide_if, 0, val);
+ ide_data_writew(&d->bus, 0, val);
}
}
@@ -3670,7 +3701,7 @@ static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
addr = (addr & 0xFFF) >> 4;
if (addr == 0) {
- retval = ide_data_readw(d->ide_if, 0);
+ retval = ide_data_readw(&d->bus, 0);
} else {
retval = 0xFFFF;
}
@@ -3690,7 +3721,7 @@ static void pmac_ide_writel (void *opaque,
val = bswap32(val);
#endif
if (addr == 0) {
- ide_data_writel(d->ide_if, 0, val);
+ ide_data_writel(&d->bus, 0, val);
}
}
@@ -3701,7 +3732,7 @@ static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
addr = (addr & 0xFFF) >> 4;
if (addr == 0) {
- retval = ide_data_readl(d->ide_if, 0);
+ retval = ide_data_readl(&d->bus, 0);
} else {
retval = 0xFFFFFFFF;
}
@@ -3726,39 +3757,31 @@ static CPUReadMemoryFunc *pmac_ide_read[] = {
static void pmac_ide_save(QEMUFile *f, void *opaque)
{
MACIOIDEState *d = opaque;
- IDEState *s = d->ide_if;
- uint8_t drive1_selected;
unsigned int i;
/* per IDE interface data */
- qemu_put_8s(f, &s->cmd);
- drive1_selected = (s->cur_drive != s);
- qemu_put_8s(f, &drive1_selected);
+ idebus_save(f, &d->bus);
/* per IDE drive data */
for(i = 0; i < 2; i++) {
- ide_save(f, &s[i]);
+ ide_save(f, &d->bus.ifs[i]);
}
}
static int pmac_ide_load(QEMUFile *f, void *opaque, int version_id)
{
MACIOIDEState *d = opaque;
- IDEState *s = d->ide_if;
- uint8_t drive1_selected;
unsigned int i;
if (version_id != 1 && version_id != 3)
return -EINVAL;
/* per IDE interface data */
- qemu_get_8s(f, &s->cmd);
- qemu_get_8s(f, &drive1_selected);
- s->cur_drive = &s[(drive1_selected != 0)];
+ idebus_load(f, &d->bus, version_id);
/* per IDE drive data */
for(i = 0; i < 2; i++) {
- ide_load(f, &s[i], version_id);
+ ide_load(f, &d->bus.ifs[i], version_id);
}
return 0;
}
@@ -3766,10 +3789,9 @@ static int pmac_ide_load(QEMUFile *f, void *opaque, int version_id)
static void pmac_ide_reset(void *opaque)
{
MACIOIDEState *d = opaque;
- IDEState *s = d->ide_if;
- ide_reset(&s[0]);
- ide_reset(&s[1]);
+ ide_reset(d->bus.ifs +0);
+ ide_reset(d->bus.ifs +1);
}
/* hd_table must contain 4 block drivers */
@@ -3782,7 +3804,7 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
int pmac_ide_memory;
d = qemu_mallocz(sizeof(MACIOIDEState));
- ide_init2(d->ide_if, hd_table[0], hd_table[1], irq);
+ ide_init2(&d->bus, hd_table[0], hd_table[1], irq);
if (dbdma)
DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
@@ -3804,31 +3826,31 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
*/
typedef struct {
- void *dev;
+ IDEBus *bus;
int shift;
} MMIOState;
static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
{
MMIOState *s = (MMIOState*)opaque;
- IDEState *ide = (IDEState*)s->dev;
+ IDEBus *bus = s->bus;
addr >>= s->shift;
if (addr & 7)
- return ide_ioport_read(ide, addr);
+ return ide_ioport_read(bus, addr);
else
- return ide_data_readw(ide, 0);
+ return ide_data_readw(bus, 0);
}
static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
MMIOState *s = (MMIOState*)opaque;
- IDEState *ide = (IDEState*)s->dev;
+ IDEBus *bus = s->bus;
addr >>= s->shift;
if (addr & 7)
- ide_ioport_write(ide, addr, val);
+ ide_ioport_write(bus, addr, val);
else
- ide_data_writew(ide, 0, val);
+ ide_data_writew(bus, 0, val);
}
static CPUReadMemoryFunc *mmio_ide_reads[] = {
@@ -3846,16 +3868,16 @@ static CPUWriteMemoryFunc *mmio_ide_writes[] = {
static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
{
MMIOState *s= (MMIOState*)opaque;
- IDEState *ide = (IDEState*)s->dev;
- return ide_status_read(ide, 0);
+ IDEBus *bus = s->bus;
+ return ide_status_read(bus, 0);
}
static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
MMIOState *s = (MMIOState*)opaque;
- IDEState *ide = (IDEState*)s->dev;
- ide_cmd_write(ide, 0, val);
+ IDEBus *bus = s->bus;
+ ide_cmd_write(bus, 0, val);
}
static CPUReadMemoryFunc *mmio_ide_status[] = {
@@ -3875,12 +3897,12 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
BlockDriverState *hd0, BlockDriverState *hd1)
{
MMIOState *s = qemu_mallocz(sizeof(MMIOState));
- IDEState *ide = qemu_mallocz(sizeof(IDEState) * 2);
+ IDEBus *bus = qemu_mallocz(sizeof(*bus));
int mem1, mem2;
- ide_init2(ide, hd0, hd1, irq);
+ ide_init2(bus, hd0, hd1, irq);
- s->dev = ide;
+ s->bus = bus;
s->shift = shift;
mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s);
@@ -3896,7 +3918,7 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
typedef struct {
- IDEState ide[2];
+ IDEBus bus;
PCMCIACardState card;
uint32_t attr_base;
uint32_t io_base;
@@ -3967,7 +3989,7 @@ static void md_reset(MicroDriveState *s)
s->pins = 0;
s->cycle = 0;
s->ctrl = 0;
- ide_reset(s->ide);
+ ide_reset(s->bus.ifs);
}
static uint8_t md_attr_read(void *opaque, uint32_t at)
@@ -4037,6 +4059,7 @@ static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
static uint16_t md_common_read(void *opaque, uint32_t at)
{
MicroDriveState *s = (MicroDriveState *) opaque;
+ IDEState *ifs;
uint16_t ret;
at -= s->io_base;
@@ -4064,13 +4087,13 @@ static uint16_t md_common_read(void *opaque, uint32_t at)
switch (at) {
case 0x0: /* Even RD Data */
case 0x8:
- return ide_data_readw(s->ide, 0);
+ return ide_data_readw(&s->bus, 0);
/* TODO: 8-bit accesses */
if (s->cycle)
ret = s->io >> 8;
else {
- s->io = ide_data_readw(s->ide, 0);
+ s->io = ide_data_readw(&s->bus, 0);
ret = s->io & 0xff;
}
s->cycle = !s->cycle;
@@ -4078,16 +4101,18 @@ static uint16_t md_common_read(void *opaque, uint32_t at)
case 0x9: /* Odd RD Data */
return s->io >> 8;
case 0xd: /* Error */
- return ide_ioport_read(s->ide, 0x1);
+ return ide_ioport_read(&s->bus, 0x1);
case 0xe: /* Alternate Status */
- if (s->ide->cur_drive->bs)
- return s->ide->cur_drive->status;
+ ifs = idebus_active_if(&s->bus);
+ if (ifs->bs)
+ return ifs->status;
else
return 0;
case 0xf: /* Device Address */
- return 0xc2 | ((~s->ide->select << 2) & 0x3c);
+ ifs = idebus_active_if(&s->bus);
+ return 0xc2 | ((~ifs->select << 2) & 0x3c);
default:
- return ide_ioport_read(s->ide, at);
+ return ide_ioport_read(&s->bus, at);
}
return 0;
@@ -4122,12 +4147,12 @@ static void md_common_write(void *opaque, uint32_t at, uint16_t value)
switch (at) {
case 0x0: /* Even WR Data */
case 0x8:
- ide_data_writew(s->ide, 0, value);
+ ide_data_writew(&s->bus, 0, value);
break;
/* TODO: 8-bit accesses */
if (s->cycle)
- ide_data_writew(s->ide, 0, s->io | (value << 8));
+ ide_data_writew(&s->bus, 0, s->io | (value << 8));
else
s->io = value & 0xff;
s->cycle = !s->cycle;
@@ -4137,7 +4162,7 @@ static void md_common_write(void *opaque, uint32_t at, uint16_t value)
s->cycle = !s->cycle;
break;
case 0xd: /* Features */
- ide_ioport_write(s->ide, 0x1, value);
+ ide_ioport_write(&s->bus, 0x1, value);
break;
case 0xe: /* Device Control */
s->ctrl = value;
@@ -4150,7 +4175,7 @@ static void md_common_write(void *opaque, uint32_t at, uint16_t value)
s->pins |= PINS_CRDY;
s->stat &= ~STAT_PWRDWN;
}
- ide_ioport_write(s->ide, at, value);
+ ide_ioport_write(&s->bus, at, value);
}
}
@@ -4158,7 +4183,6 @@ static void md_save(QEMUFile *f, void *opaque)
{
MicroDriveState *s = (MicroDriveState *) opaque;
int i;
- uint8_t drive1_selected;
qemu_put_8s(f, &s->opt);
qemu_put_8s(f, &s->stat);
@@ -4168,19 +4192,16 @@ static void md_save(QEMUFile *f, void *opaque)
qemu_put_be16s(f, &s->io);
qemu_put_byte(f, s->cycle);
- drive1_selected = (s->ide->cur_drive != s->ide);
- qemu_put_8s(f, &s->ide->cmd);
- qemu_put_8s(f, &drive1_selected);
+ idebus_save(f, &s->bus);
for (i = 0; i < 2; i ++)
- ide_save(f, &s->ide[i]);
+ ide_save(f, &s->bus.ifs[i]);
}
static int md_load(QEMUFile *f, void *opaque, int version_id)
{
MicroDriveState *s = (MicroDriveState *) opaque;
int i;
- uint8_t drive1_selected;
if (version_id != 0 && version_id != 3)
return -EINVAL;
@@ -4193,12 +4214,10 @@ static int md_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_be16s(f, &s->io);
s->cycle = qemu_get_byte(f);
- qemu_get_8s(f, &s->ide->cmd);
- qemu_get_8s(f, &drive1_selected);
- s->ide->cur_drive = &s->ide[(drive1_selected != 0)];
+ idebus_load(f, &s->bus, version_id);
for (i = 0; i < 2; i ++)
- ide_load(f, &s->ide[i], version_id);
+ ide_load(f, &s->bus.ifs[i], version_id);
return 0;
}
@@ -4424,10 +4443,10 @@ PCMCIACardState *dscm1xxxx_init(BlockDriverState *bdrv)
md->card.cis = dscm1xxxx_cis;
md->card.cis_len = sizeof(dscm1xxxx_cis);
- ide_init2(md->ide, bdrv, NULL, qemu_allocate_irqs(md_set_irq, md, 1)[0]);
- md->ide->is_cf = 1;
- md->ide->mdata_size = METADATA_SIZE;
- md->ide->mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);
+ ide_init2(&md->bus, bdrv, NULL, qemu_allocate_irqs(md_set_irq, md, 1)[0]);
+ md->bus.ifs[0].is_cf = 1;
+ md->bus.ifs[0].mdata_size = METADATA_SIZE;
+ md->bus.ifs[0].mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);
register_savevm("microdrive", -1, 3, md_save, md_load, md);
--
1.6.2.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Qemu-devel] Re: [PATCH 1/8] ide: add IDEBus struct, cleanups
2009-08-18 16:06 ` [Qemu-devel] [PATCH 1/8] ide: add IDEBus struct, cleanups Gerd Hoffmann
@ 2009-08-19 9:49 ` Juan Quintela
0 siblings, 0 replies; 15+ messages in thread
From: Juan Quintela @ 2009-08-19 9:49 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: qemu-devel
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reply-to: quintela@redhat.com
Gerd Hoffmann <kraxel@redhat.com> wrote:
>
> switch(addr) {
> case 0:
> break;
> case 1:
> - ide_clear_hob(ide_if);
> + ide_clear_hob(bus);
> /* NOTE: data is written to the two drives */
> - ide_if[0].hob_feature = ide_if[0].feature;
> - ide_if[1].hob_feature = ide_if[1].feature;
> - ide_if[0].feature = val;
> - ide_if[1].feature = val;
> + bus->ifs[0].hob_feature = bus->ifs[0].feature;
> + bus->ifs[1].hob_feature = bus->ifs[1].feature;
> + bus->ifs[0].feature = val;
> + bus->ifs[1].feature = val;
> break;
Once that you are here, can you fix the indentantion, please?
(rest of this case have this strange indentantion)
That is a nitpit, and already exist in previous code.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH 2/8] ide: split away ide-isa.c
2009-08-18 16:06 [Qemu-devel] [PATCH 0/8] ide: cleanup and splitting Gerd Hoffmann
2009-08-18 16:06 ` [Qemu-devel] [PATCH 1/8] ide: add IDEBus struct, cleanups Gerd Hoffmann
@ 2009-08-18 16:06 ` Gerd Hoffmann
2009-08-19 9:53 ` [Qemu-devel] " Juan Quintela
2009-08-18 16:06 ` [Qemu-devel] [PATCH 3/8] ide: add save/restore support for isa Gerd Hoffmann
` (6 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Gerd Hoffmann @ 2009-08-18 16:06 UTC (permalink / raw)
To: qemu-devel; +Cc: Gerd Hoffmann
create ide.h and ide-internal header files. ide-internal.h is supposed
to be used by ide*.c only.
create ide-isa.c and place isa bus support there.
only build ide-isa support for platforms using it.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
Makefile.target | 7 ++-
hw/ide-internal.h | 97 +++++++++++++++++++++++++++++++++++++++++++++++
hw/ide-isa.c | 45 ++++++++++++++++++++++
hw/ide.c | 109 ++---------------------------------------------------
hw/ide.h | 10 +++++
hw/mips_r4k.c | 1 +
hw/pc.c | 1 +
hw/pc.h | 2 -
hw/ppc_prep.c | 1 +
9 files changed, 163 insertions(+), 110 deletions(-)
create mode 100644 hw/ide-internal.h
create mode 100644 hw/ide-isa.c
create mode 100644 hw/ide.h
diff --git a/Makefile.target b/Makefile.target
index 3f5d24a..f4d12c6 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -183,14 +183,14 @@ obj-y += e1000.o
obj-y += wdt_ib700.o wdt_i6300esb.o
# Hardware support
-obj-i386-y = ide.o pckbd.o vga.o $(sound-obj-y) dma.o isa-bus.o
+obj-i386-y = ide.o ide-isa.o pckbd.o vga.o $(sound-obj-y) dma.o isa-bus.o
obj-i386-y += fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
obj-i386-y += cirrus_vga.o apic.o ioapic.o parallel.o acpi.o piix_pci.o
obj-i386-y += usb-uhci.o vmmouse.o vmport.o vmware_vga.o hpet.o
obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o
# shared objects
-obj-ppc-y = ppc.o ide.o vga.o $(sound-obj-y) dma.o isa-bus.o openpic.o
+obj-ppc-y = ppc.o ide.o ide-isa.o vga.o $(sound-obj-y) dma.o isa-bus.o openpic.o
# PREP target
obj-ppc-y += pckbd.o serial.o i8259.o i8254.o fdc.o mc146818rtc.o
obj-ppc-y += prep_pci.o ppc_prep.o
@@ -211,7 +211,8 @@ obj-ppc-$(CONFIG_FDT) += device_tree.o
obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-mips-y += mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o rc4030.o
obj-mips-y += g364fb.o jazz_led.o dp8393x.o
-obj-mips-y += ide.o gt64xxx.o pckbd.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
+obj-mips-y += ide.o ide-isa.o
+obj-mips-y += gt64xxx.o pckbd.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
obj-mips-y += piix_pci.o parallel.o cirrus_vga.o isa-bus.o pcspk.o $(sound-obj-y)
obj-mips-y += mipsnet.o
obj-mips-y += pflash_cfi01.o
diff --git a/hw/ide-internal.h b/hw/ide-internal.h
new file mode 100644
index 0000000..c2ccb11
--- /dev/null
+++ b/hw/ide-internal.h
@@ -0,0 +1,97 @@
+#ifndef HW_IDE_INTERNAL_H
+#define HW_IDE_INTERNAL_H
+
+#include "ide.h"
+
+typedef struct IDEBus IDEBus;
+typedef struct IDEState IDEState;
+typedef struct BMDMAState BMDMAState;
+
+typedef void EndTransferFunc(IDEState *);
+
+/* NOTE: IDEState represents in fact one drive */
+struct IDEState {
+ IDEBus *bus;
+ uint8_t unit;
+ /* ide config */
+ int is_cdrom;
+ int is_cf;
+ int cylinders, heads, sectors;
+ int64_t nb_sectors;
+ int mult_sectors;
+ int identify_set;
+ uint16_t identify_data[256];
+ qemu_irq irq;
+ int drive_serial;
+ char drive_serial_str[21];
+ /* ide regs */
+ uint8_t feature;
+ uint8_t error;
+ uint32_t nsector;
+ uint8_t sector;
+ uint8_t lcyl;
+ uint8_t hcyl;
+ /* other part of tf for lba48 support */
+ uint8_t hob_feature;
+ uint8_t hob_nsector;
+ uint8_t hob_sector;
+ uint8_t hob_lcyl;
+ uint8_t hob_hcyl;
+
+ uint8_t select;
+ uint8_t status;
+
+ /* 0x3f6 command, only meaningful for drive 0 */
+ uint8_t cmd;
+ /* set for lba48 access */
+ uint8_t lba48;
+ BlockDriverState *bs;
+ /* ATAPI specific */
+ uint8_t sense_key;
+ uint8_t asc;
+ uint8_t cdrom_changed;
+ int packet_transfer_size;
+ int elementary_transfer_size;
+ int io_buffer_index;
+ int lba;
+ int cd_sector_size;
+ int atapi_dma; /* true if dma is requested for the packet cmd */
+ /* ATA DMA state */
+ int io_buffer_size;
+ QEMUSGList sg;
+ /* PIO transfer handling */
+ int req_nb_sectors; /* number of sectors per interrupt */
+ EndTransferFunc *end_transfer_func;
+ uint8_t *data_ptr;
+ uint8_t *data_end;
+ uint8_t *io_buffer;
+ QEMUTimer *sector_write_timer; /* only used for win2k install hack */
+ uint32_t irq_count; /* counts IRQs when using win2k install hack */
+ /* CF-ATA extended error */
+ uint8_t ext_error;
+ /* CF-ATA metadata storage */
+ uint32_t mdata_size;
+ uint8_t *mdata_storage;
+ int media_changed;
+ /* for pmac */
+ int is_read;
+};
+
+struct IDEBus {
+ BusState qbus;
+ BMDMAState *bmdma;
+ IDEState ifs[2];
+ uint8_t unit;
+};
+
+static inline IDEState *idebus_active_if(IDEBus *bus)
+{
+ return bus->ifs + bus->unit;
+}
+
+/* ide.c */
+void ide_init2(IDEBus *bus, BlockDriverState *hd0, BlockDriverState *hd1,
+ qemu_irq irq);
+void ide_init_ioport(IDEBus *bus, int iobase, int iobase2);
+
+#endif /* HW_IDE_INTERNAL_H */
diff --git a/hw/ide-isa.c b/hw/ide-isa.c
new file mode 100644
index 0000000..2d65825
--- /dev/null
+++ b/hw/ide-isa.c
@@ -0,0 +1,45 @@
+/*
+ * QEMU IDE disk and CD/DVD-ROM Emulator
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2006 Openedhand Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "pc.h"
+#include "block.h"
+#include "block_int.h"
+#include "sysemu.h"
+#include "dma.h"
+#include "ide-internal.h"
+
+/***********************************************************/
+/* ISA IDE definitions */
+
+void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
+ BlockDriverState *hd0, BlockDriverState *hd1)
+{
+ IDEBus *bus;
+
+ bus = qemu_mallocz(sizeof(*bus));
+
+ ide_init2(bus, hd0, hd1, irq);
+ ide_init_ioport(bus, iobase, iobase2);
+}
diff --git a/hw/ide.c b/hw/ide.c
index f5803f1..879196e 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -35,11 +35,7 @@
#include "mac_dbdma.h"
#include "sh.h"
#include "dma.h"
-#include "ide.h"
-
-typedef struct IDEBus IDEBus;
-typedef struct IDEState IDEState;
-typedef struct BMDMAState BMDMAState;
+#include "ide-internal.h"
/* debug IDE devices */
//#define DEBUG_IDE
@@ -377,83 +373,6 @@ typedef struct BMDMAState BMDMAState;
#define SENSE_ILLEGAL_REQUEST 5
#define SENSE_UNIT_ATTENTION 6
-typedef void EndTransferFunc(IDEState *);
-
-/* NOTE: IDEState represents in fact one drive */
-struct IDEState {
- IDEBus *bus;
- uint8_t unit;
- /* ide config */
- int is_cdrom;
- int is_cf;
- int cylinders, heads, sectors;
- int64_t nb_sectors;
- int mult_sectors;
- int identify_set;
- uint16_t identify_data[256];
- qemu_irq irq;
- int drive_serial;
- char drive_serial_str[21];
- /* ide regs */
- uint8_t feature;
- uint8_t error;
- uint32_t nsector;
- uint8_t sector;
- uint8_t lcyl;
- uint8_t hcyl;
- /* other part of tf for lba48 support */
- uint8_t hob_feature;
- uint8_t hob_nsector;
- uint8_t hob_sector;
- uint8_t hob_lcyl;
- uint8_t hob_hcyl;
-
- uint8_t select;
- uint8_t status;
-
- /* 0x3f6 command, only meaningful for drive 0 */
- uint8_t cmd;
- /* set for lba48 access */
- uint8_t lba48;
- BlockDriverState *bs;
- /* ATAPI specific */
- uint8_t sense_key;
- uint8_t asc;
- uint8_t cdrom_changed;
- int packet_transfer_size;
- int elementary_transfer_size;
- int io_buffer_index;
- int lba;
- int cd_sector_size;
- int atapi_dma; /* true if dma is requested for the packet cmd */
- /* ATA DMA state */
- int io_buffer_size;
- QEMUSGList sg;
- /* PIO transfer handling */
- int req_nb_sectors; /* number of sectors per interrupt */
- EndTransferFunc *end_transfer_func;
- uint8_t *data_ptr;
- uint8_t *data_end;
- uint8_t *io_buffer;
- QEMUTimer *sector_write_timer; /* only used for win2k install hack */
- uint32_t irq_count; /* counts IRQs when using win2k install hack */
- /* CF-ATA extended error */
- uint8_t ext_error;
- /* CF-ATA metadata storage */
- uint32_t mdata_size;
- uint8_t *mdata_storage;
- int media_changed;
- /* for pmac */
- int is_read;
-};
-
-struct IDEBus {
- BusState qbus;
- BMDMAState *bmdma;
- IDEState ifs[2];
- uint8_t unit;
-};
-
/* XXX: DVDs that could fit on a CD will be reported as a CD */
static inline int media_present(IDEState *s)
{
@@ -527,11 +446,6 @@ static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
return bmdma->bus->ifs + bmdma->unit;
}
-static inline IDEState *idebus_active_if(IDEBus *bus)
-{
- return bus->ifs + bus->unit;
-}
-
static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb);
static void ide_dma_restart(IDEState *s);
static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret);
@@ -2829,9 +2743,8 @@ static void ide_reset(IDEState *s)
s->media_changed = 0;
}
-static void ide_init2(IDEBus *bus,
- BlockDriverState *hd0, BlockDriverState *hd1,
- qemu_irq irq)
+void ide_init2(IDEBus *bus, BlockDriverState *hd0, BlockDriverState *hd1,
+ qemu_irq irq)
{
IDEState *s;
static int drive_serial = 1;
@@ -2870,7 +2783,7 @@ static void ide_init2(IDEBus *bus,
}
}
-static void ide_init_ioport(IDEBus *bus, int iobase, int iobase2)
+void ide_init_ioport(IDEBus *bus, int iobase, int iobase2)
{
register_ioport_write(iobase, 8, 1, ide_ioport_write, bus);
register_ioport_read(iobase, 8, 1, ide_ioport_read, bus);
@@ -2969,20 +2882,6 @@ static void idebus_load(QEMUFile* f, IDEBus *bus, int version_id)
}
/***********************************************************/
-/* ISA IDE definitions */
-
-void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
- BlockDriverState *hd0, BlockDriverState *hd1)
-{
- IDEBus *bus;
-
- bus = qemu_mallocz(sizeof(*bus));
-
- ide_init2(bus, hd0, hd1, irq);
- ide_init_ioport(bus, iobase, iobase2);
-}
-
-/***********************************************************/
/* PCI IDE definitions */
static void cmd646_update_irq(PCIIDEState *d);
diff --git a/hw/ide.h b/hw/ide.h
new file mode 100644
index 0000000..73ef93e
--- /dev/null
+++ b/hw/ide.h
@@ -0,0 +1,10 @@
+#ifndef HW_IDE_H
+#define HW_IDE_H
+
+#include "qdev.h"
+
+/* ide-isa.c */
+void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
+ BlockDriverState *hd0, BlockDriverState *hd1);
+
+#endif /* HW_IDE_H */
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 476612c..9e31501 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -17,6 +17,7 @@
#include "flash.h"
#include "qemu-log.h"
#include "mips-bios.h"
+#include "ide.h"
#define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fffffff)
diff --git a/hw/pc.c b/hw/pc.c
index cc6e7e8..817b922 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -36,6 +36,7 @@
#include "hpet_emul.h"
#include "watchdog.h"
#include "smbios.h"
+#include "ide.h"
/* output Bochs bios info messages */
//#define DEBUG_BIOS
diff --git a/hw/pc.h b/hw/pc.h
index 9fbae20..a8b593f 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -152,8 +152,6 @@ void pci_cirrus_vga_init(PCIBus *bus);
void isa_cirrus_vga_init(void);
/* ide.c */
-void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
- BlockDriverState *hd0, BlockDriverState *hd1);
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
int secondary_ide_enabled);
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 97190a2..6fd176f 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -32,6 +32,7 @@
#include "ppc.h"
#include "boards.h"
#include "qemu-log.h"
+#include "ide.h"
//#define HARD_DEBUG_PPC_IO
//#define DEBUG_PPC_IO
--
1.6.2.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Qemu-devel] Re: [PATCH 2/8] ide: split away ide-isa.c
2009-08-18 16:06 ` [Qemu-devel] [PATCH 2/8] ide: split away ide-isa.c Gerd Hoffmann
@ 2009-08-19 9:53 ` Juan Quintela
0 siblings, 0 replies; 15+ messages in thread
From: Juan Quintela @ 2009-08-19 9:53 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: qemu-devel
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reply-to: quintela@redhat.com
Gerd Hoffmann <kraxel@redhat.com> wrote:
> create ide.h and ide-internal header files. ide-internal.h is supposed
> to be used by ide*.c only.
>
> create ide-isa.c and place isa bus support there.
> only build ide-isa support for platforms using it.
> --- /dev/null
> +++ b/hw/ide-internal.h
> @@ -0,0 +1,97 @@
> +#ifndef HW_IDE_INTERNAL_H
> +#define HW_IDE_INTERNAL_H
> +
Add a comment stating something in the lines of:
/* IDE internal definitions
if you are not an ide-*.c file, you should not load it
*/
> diff --git a/hw/ide-isa.c b/hw/ide-isa.c
> new file mode 100644
> index 0000000..2d65825
> --- /dev/null
> +++ b/hw/ide-isa.c
> @@ -0,0 +1,45 @@
> +/*
> + * QEMU IDE disk and CD/DVD-ROM Emulator
> + *
QEMU IDE Bus abstraction?
Again, only nitpits, agreed with the reorganization.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH 3/8] ide: add save/restore support for isa
2009-08-18 16:06 [Qemu-devel] [PATCH 0/8] ide: cleanup and splitting Gerd Hoffmann
2009-08-18 16:06 ` [Qemu-devel] [PATCH 1/8] ide: add IDEBus struct, cleanups Gerd Hoffmann
2009-08-18 16:06 ` [Qemu-devel] [PATCH 2/8] ide: split away ide-isa.c Gerd Hoffmann
@ 2009-08-18 16:06 ` Gerd Hoffmann
2009-08-18 16:06 ` [Qemu-devel] [PATCH 4/8] ide: split away ide-pci.c Gerd Hoffmann
` (5 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Gerd Hoffmann @ 2009-08-18 16:06 UTC (permalink / raw)
To: qemu-devel; +Cc: Gerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
hw/ide-internal.h | 5 +++++
hw/ide-isa.c | 33 +++++++++++++++++++++++++++++----
hw/ide.c | 8 ++++----
3 files changed, 38 insertions(+), 8 deletions(-)
diff --git a/hw/ide-internal.h b/hw/ide-internal.h
index c2ccb11..d4a4947 100644
--- a/hw/ide-internal.h
+++ b/hw/ide-internal.h
@@ -90,6 +90,11 @@ static inline IDEState *idebus_active_if(IDEBus *bus)
}
/* ide.c */
+void ide_save(QEMUFile* f, IDEState *s);
+void ide_load(QEMUFile* f, IDEState *s, int version_id);
+void idebus_save(QEMUFile* f, IDEBus *bus);
+void idebus_load(QEMUFile* f, IDEBus *bus, int version_id);
+
void ide_init2(IDEBus *bus, BlockDriverState *hd0, BlockDriverState *hd1,
qemu_irq irq);
void ide_init_ioport(IDEBus *bus, int iobase, int iobase2);
diff --git a/hw/ide-isa.c b/hw/ide-isa.c
index 2d65825..38ba6f9 100644
--- a/hw/ide-isa.c
+++ b/hw/ide-isa.c
@@ -33,13 +33,38 @@
/***********************************************************/
/* ISA IDE definitions */
+typedef struct ISAIDEState {
+ IDEBus *bus;
+} ISAIDEState;
+
+static void isa_ide_save(QEMUFile* f, void *opaque)
+{
+ ISAIDEState *s = opaque;
+
+ idebus_save(f, s->bus);
+ ide_save(f, &s->bus->ifs[0]);
+ ide_save(f, &s->bus->ifs[1]);
+}
+
+static int isa_ide_load(QEMUFile* f, void *opaque, int version_id)
+{
+ ISAIDEState *s = opaque;
+
+ idebus_load(f, s->bus, version_id);
+ ide_load(f, &s->bus->ifs[0], version_id);
+ ide_load(f, &s->bus->ifs[1], version_id);
+ return 0;
+}
+
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
BlockDriverState *hd0, BlockDriverState *hd1)
{
- IDEBus *bus;
+ ISAIDEState *s;
- bus = qemu_mallocz(sizeof(*bus));
+ s = qemu_mallocz(sizeof(*s));
+ s->bus = qemu_mallocz(sizeof(IDEBus));
- ide_init2(bus, hd0, hd1, irq);
- ide_init_ioport(bus, iobase, iobase2);
+ ide_init2(s->bus, hd0, hd1, irq);
+ ide_init_ioport(s->bus, iobase, iobase2);
+ register_savevm("isa-ide", 0, 3, isa_ide_save, isa_ide_load, s);
}
diff --git a/hw/ide.c b/hw/ide.c
index 879196e..5fb42b7 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -2800,7 +2800,7 @@ void ide_init_ioport(IDEBus *bus, int iobase, int iobase2)
}
/* save per IDE drive data */
-static void ide_save(QEMUFile* f, IDEState *s)
+void ide_save(QEMUFile* f, IDEState *s)
{
qemu_put_be32(f, s->mult_sectors);
qemu_put_be32(f, s->identify_set);
@@ -2829,7 +2829,7 @@ static void ide_save(QEMUFile* f, IDEState *s)
}
/* load per IDE drive data */
-static void ide_load(QEMUFile* f, IDEState *s, int version_id)
+void ide_load(QEMUFile* f, IDEState *s, int version_id)
{
s->mult_sectors=qemu_get_be32(f);
s->identify_set=qemu_get_be32(f);
@@ -2863,14 +2863,14 @@ static void ide_load(QEMUFile* f, IDEState *s, int version_id)
/* XXX: if a transfer is pending, we do not save it yet */
}
-static void idebus_save(QEMUFile* f, IDEBus *bus)
+void idebus_save(QEMUFile* f, IDEBus *bus)
{
IDEState *s = idebus_active_if(bus);
qemu_put_8s(f, &s->cmd);
qemu_put_8s(f, &bus->unit);
}
-static void idebus_load(QEMUFile* f, IDEBus *bus, int version_id)
+void idebus_load(QEMUFile* f, IDEBus *bus, int version_id)
{
IDEState *s;
uint8_t cmd;
--
1.6.2.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Qemu-devel] [PATCH 4/8] ide: split away ide-pci.c
2009-08-18 16:06 [Qemu-devel] [PATCH 0/8] ide: cleanup and splitting Gerd Hoffmann
` (2 preceding siblings ...)
2009-08-18 16:06 ` [Qemu-devel] [PATCH 3/8] ide: add save/restore support for isa Gerd Hoffmann
@ 2009-08-18 16:06 ` Gerd Hoffmann
2009-08-18 16:06 ` [Qemu-devel] [PATCH 5/8] ide: split away ide-macio.c Gerd Hoffmann
` (4 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Gerd Hoffmann @ 2009-08-18 16:06 UTC (permalink / raw)
To: qemu-devel; +Cc: Gerd Hoffmann
create ide-pci.c and place pci bus support there.
only build ide-pci support for platforms using it.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
Makefile.target | 9 +-
hw/ide-internal.h | 49 +++++
hw/ide-pci.c | 519 ++++++++++++++++++++++++++++++++++++++++++++++++++
hw/ide.c | 540 +----------------------------------------------------
hw/ide.h | 8 +
hw/mips_malta.c | 1 +
hw/pc.h | 8 -
hw/ppc_newworld.c | 1 +
hw/ppc_oldworld.c | 1 +
hw/sun4u.c | 1 +
10 files changed, 595 insertions(+), 542 deletions(-)
create mode 100644 hw/ide-pci.c
diff --git a/Makefile.target b/Makefile.target
index f4d12c6..fbc76d4 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -183,14 +183,15 @@ obj-y += e1000.o
obj-y += wdt_ib700.o wdt_i6300esb.o
# Hardware support
-obj-i386-y = ide.o ide-isa.o pckbd.o vga.o $(sound-obj-y) dma.o isa-bus.o
+obj-i386-y = ide.o ide-isa.o ide-pci.o pckbd.o vga.o $(sound-obj-y) dma.o isa-bus.o
obj-i386-y += fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
obj-i386-y += cirrus_vga.o apic.o ioapic.o parallel.o acpi.o piix_pci.o
obj-i386-y += usb-uhci.o vmmouse.o vmport.o vmware_vga.o hpet.o
obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o
# shared objects
-obj-ppc-y = ppc.o ide.o ide-isa.o vga.o $(sound-obj-y) dma.o isa-bus.o openpic.o
+obj-ppc-y = ppc.o ide.o ide-isa.o ide-pci.o
+obj-ppc-y += vga.o $(sound-obj-y) dma.o isa-bus.o openpic.o
# PREP target
obj-ppc-y += pckbd.o serial.o i8259.o i8254.o fdc.o mc146818rtc.o
obj-ppc-y += prep_pci.o ppc_prep.o
@@ -211,7 +212,7 @@ obj-ppc-$(CONFIG_FDT) += device_tree.o
obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-mips-y += mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o rc4030.o
obj-mips-y += g364fb.o jazz_led.o dp8393x.o
-obj-mips-y += ide.o ide-isa.o
+obj-mips-y += ide.o ide-isa.o ide-pci.o
obj-mips-y += gt64xxx.o pckbd.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
obj-mips-y += piix_pci.o parallel.o cirrus_vga.o isa-bus.o pcspk.o $(sound-obj-y)
obj-mips-y += mipsnet.o
@@ -243,7 +244,7 @@ obj-cris-y += etraxfs_ser.o
obj-cris-y += pflash_cfi02.o
ifeq ($(TARGET_ARCH), sparc64)
-obj-sparc-y = sun4u.o ide.o isa-bus.o pckbd.o vga.o apb_pci.o
+obj-sparc-y = sun4u.o ide.o ide-pci.o isa-bus.o pckbd.o vga.o apb_pci.o
obj-sparc-y += fdc.o mc146818rtc.o serial.o
obj-sparc-y += cirrus_vga.o parallel.o
else
diff --git a/hw/ide-internal.h b/hw/ide-internal.h
index d4a4947..47e92cf 100644
--- a/hw/ide-internal.h
+++ b/hw/ide-internal.h
@@ -84,17 +84,66 @@ struct IDEBus {
uint8_t unit;
};
+#define BM_STATUS_DMAING 0x01
+#define BM_STATUS_ERROR 0x02
+#define BM_STATUS_INT 0x04
+#define BM_STATUS_DMA_RETRY 0x08
+#define BM_STATUS_PIO_RETRY 0x10
+
+#define BM_CMD_START 0x01
+#define BM_CMD_READ 0x08
+
+struct BMDMAState {
+ uint8_t cmd;
+ uint8_t status;
+ uint32_t addr;
+
+ struct PCIIDEState *pci_dev;
+ IDEBus *bus;
+ /* current transfer state */
+ uint32_t cur_addr;
+ uint32_t cur_prd_last;
+ uint32_t cur_prd_addr;
+ uint32_t cur_prd_len;
+ uint8_t unit;
+ BlockDriverCompletionFunc *dma_cb;
+ BlockDriverAIOCB *aiocb;
+ struct iovec iov;
+ QEMUIOVector qiov;
+ int64_t sector_num;
+ uint32_t nsector;
+ QEMUBH *bh;
+};
+
static inline IDEState *idebus_active_if(IDEBus *bus)
{
return bus->ifs + bus->unit;
}
+static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
+{
+ assert(bmdma->unit != -1);
+ return bmdma->bus->ifs + bmdma->unit;
+}
+
/* ide.c */
void ide_save(QEMUFile* f, IDEState *s);
void ide_load(QEMUFile* f, IDEState *s, int version_id);
void idebus_save(QEMUFile* f, IDEBus *bus);
void idebus_load(QEMUFile* f, IDEBus *bus, int version_id);
+void ide_dma_cancel(BMDMAState *bm);
+void ide_dma_restart_cb(void *opaque, int running, int reason);
+
+void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val);
+uint32_t ide_ioport_read(void *opaque, uint32_t addr1);
+uint32_t ide_status_read(void *opaque, uint32_t addr);
+void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val);
+void ide_data_writew(void *opaque, uint32_t addr, uint32_t val);
+uint32_t ide_data_readw(void *opaque, uint32_t addr);
+void ide_data_writel(void *opaque, uint32_t addr, uint32_t val);
+uint32_t ide_data_readl(void *opaque, uint32_t addr);
+
void ide_init2(IDEBus *bus, BlockDriverState *hd0, BlockDriverState *hd1,
qemu_irq irq);
void ide_init_ioport(IDEBus *bus, int iobase, int iobase2);
diff --git a/hw/ide-pci.c b/hw/ide-pci.c
new file mode 100644
index 0000000..ddf05b1
--- /dev/null
+++ b/hw/ide-pci.c
@@ -0,0 +1,519 @@
+/*
+ * QEMU IDE disk and CD/DVD-ROM Emulator
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2006 Openedhand Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "pc.h"
+#include "block.h"
+#include "block_int.h"
+#include "sysemu.h"
+#include "dma.h"
+#include "pci.h"
+#include "ide-internal.h"
+
+/***********************************************************/
+/* PCI IDE definitions */
+
+/* CMD646 specific */
+#define MRDMODE 0x71
+#define MRDMODE_INTR_CH0 0x04
+#define MRDMODE_INTR_CH1 0x08
+#define MRDMODE_BLK_CH0 0x10
+#define MRDMODE_BLK_CH1 0x20
+#define UDIDETCR0 0x73
+#define UDIDETCR1 0x7B
+
+#define IDE_TYPE_PIIX3 0
+#define IDE_TYPE_CMD646 1
+#define IDE_TYPE_PIIX4 2
+
+typedef struct PCIIDEState {
+ PCIDevice dev;
+ IDEBus bus[2];
+ BMDMAState bmdma[2];
+ int type; /* see IDE_TYPE_xxx */
+} PCIIDEState;
+
+static void cmd646_update_irq(PCIIDEState *d);
+
+static void ide_map(PCIDevice *pci_dev, int region_num,
+ uint32_t addr, uint32_t size, int type)
+{
+ PCIIDEState *d = (PCIIDEState *)pci_dev;
+ IDEBus *bus;
+
+ if (region_num <= 3) {
+ bus = &d->bus[(region_num >> 1)];
+ if (region_num & 1) {
+ register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
+ register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
+ } else {
+ register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
+ register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
+
+ /* data ports */
+ register_ioport_write(addr, 2, 2, ide_data_writew, bus);
+ register_ioport_read(addr, 2, 2, ide_data_readw, bus);
+ register_ioport_write(addr, 4, 4, ide_data_writel, bus);
+ register_ioport_read(addr, 4, 4, ide_data_readl, bus);
+ }
+ }
+}
+
+static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ BMDMAState *bm = opaque;
+#ifdef DEBUG_IDE
+ printf("%s: 0x%08x\n", __func__, val);
+#endif
+ if (!(val & BM_CMD_START)) {
+ /* XXX: do it better */
+ ide_dma_cancel(bm);
+ bm->cmd = val & 0x09;
+ } else {
+ if (!(bm->status & BM_STATUS_DMAING)) {
+ bm->status |= BM_STATUS_DMAING;
+ /* start dma transfer if possible */
+ if (bm->dma_cb)
+ bm->dma_cb(bm, 0);
+ }
+ bm->cmd = val & 0x09;
+ }
+}
+
+static uint32_t bmdma_readb(void *opaque, uint32_t addr)
+{
+ BMDMAState *bm = opaque;
+ PCIIDEState *pci_dev;
+ uint32_t val;
+
+ switch(addr & 3) {
+ case 0:
+ val = bm->cmd;
+ break;
+ case 1:
+ pci_dev = bm->pci_dev;
+ if (pci_dev->type == IDE_TYPE_CMD646) {
+ val = pci_dev->dev.config[MRDMODE];
+ } else {
+ val = 0xff;
+ }
+ break;
+ case 2:
+ val = bm->status;
+ break;
+ case 3:
+ pci_dev = bm->pci_dev;
+ if (pci_dev->type == IDE_TYPE_CMD646) {
+ if (bm == &pci_dev->bmdma[0])
+ val = pci_dev->dev.config[UDIDETCR0];
+ else
+ val = pci_dev->dev.config[UDIDETCR1];
+ } else {
+ val = 0xff;
+ }
+ break;
+ default:
+ val = 0xff;
+ break;
+ }
+#ifdef DEBUG_IDE
+ printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
+#endif
+ return val;
+}
+
+static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ BMDMAState *bm = opaque;
+ PCIIDEState *pci_dev;
+#ifdef DEBUG_IDE
+ printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
+#endif
+ switch(addr & 3) {
+ case 1:
+ pci_dev = bm->pci_dev;
+ if (pci_dev->type == IDE_TYPE_CMD646) {
+ pci_dev->dev.config[MRDMODE] =
+ (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
+ cmd646_update_irq(pci_dev);
+ }
+ break;
+ case 2:
+ bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
+ break;
+ case 3:
+ pci_dev = bm->pci_dev;
+ if (pci_dev->type == IDE_TYPE_CMD646) {
+ if (bm == &pci_dev->bmdma[0])
+ pci_dev->dev.config[UDIDETCR0] = val;
+ else
+ pci_dev->dev.config[UDIDETCR1] = val;
+ }
+ break;
+ }
+}
+
+static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr)
+{
+ BMDMAState *bm = opaque;
+ uint32_t val;
+ val = (bm->addr >> ((addr & 3) * 8)) & 0xff;
+#ifdef DEBUG_IDE
+ printf("%s: 0x%08x\n", __func__, val);
+#endif
+ return val;
+}
+
+static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ BMDMAState *bm = opaque;
+ int shift = (addr & 3) * 8;
+#ifdef DEBUG_IDE
+ printf("%s: 0x%08x\n", __func__, val);
+#endif
+ bm->addr &= ~(0xFF << shift);
+ bm->addr |= ((val & 0xFF) << shift) & ~3;
+ bm->cur_addr = bm->addr;
+}
+
+static uint32_t bmdma_addr_readw(void *opaque, uint32_t addr)
+{
+ BMDMAState *bm = opaque;
+ uint32_t val;
+ val = (bm->addr >> ((addr & 3) * 8)) & 0xffff;
+#ifdef DEBUG_IDE
+ printf("%s: 0x%08x\n", __func__, val);
+#endif
+ return val;
+}
+
+static void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val)
+{
+ BMDMAState *bm = opaque;
+ int shift = (addr & 3) * 8;
+#ifdef DEBUG_IDE
+ printf("%s: 0x%08x\n", __func__, val);
+#endif
+ bm->addr &= ~(0xFFFF << shift);
+ bm->addr |= ((val & 0xFFFF) << shift) & ~3;
+ bm->cur_addr = bm->addr;
+}
+
+static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
+{
+ BMDMAState *bm = opaque;
+ uint32_t val;
+ val = bm->addr;
+#ifdef DEBUG_IDE
+ printf("%s: 0x%08x\n", __func__, val);
+#endif
+ return val;
+}
+
+static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
+{
+ BMDMAState *bm = opaque;
+#ifdef DEBUG_IDE
+ printf("%s: 0x%08x\n", __func__, val);
+#endif
+ bm->addr = val & ~3;
+ bm->cur_addr = bm->addr;
+}
+
+static void bmdma_map(PCIDevice *pci_dev, int region_num,
+ uint32_t addr, uint32_t size, int type)
+{
+ PCIIDEState *d = (PCIIDEState *)pci_dev;
+ int i;
+
+ for(i = 0;i < 2; i++) {
+ BMDMAState *bm = &d->bmdma[i];
+ d->bus[i].bmdma = bm;
+ bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev);
+ bm->bus = d->bus+i;
+ qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
+
+ register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
+
+ register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
+ register_ioport_read(addr, 4, 1, bmdma_readb, bm);
+
+ register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
+ register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
+ register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
+ register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
+ register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
+ register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
+ addr += 8;
+ }
+}
+
+static void pci_ide_save(QEMUFile* f, void *opaque)
+{
+ PCIIDEState *d = opaque;
+ int i;
+
+ pci_device_save(&d->dev, f);
+
+ for(i = 0; i < 2; i++) {
+ BMDMAState *bm = &d->bmdma[i];
+ uint8_t ifidx;
+ qemu_put_8s(f, &bm->cmd);
+ qemu_put_8s(f, &bm->status);
+ qemu_put_be32s(f, &bm->addr);
+ qemu_put_sbe64s(f, &bm->sector_num);
+ qemu_put_be32s(f, &bm->nsector);
+ ifidx = bm->unit + 2*i;
+ qemu_put_8s(f, &ifidx);
+ /* XXX: if a transfer is pending, we do not save it yet */
+ }
+
+ /* per IDE interface data */
+ for(i = 0; i < 2; i++) {
+ idebus_save(f, &d->bus[i]);
+ }
+
+ /* per IDE drive data */
+ for(i = 0; i < 2; i++) {
+ ide_save(f, &d->bus[i].ifs[0]);
+ ide_save(f, &d->bus[i].ifs[1]);
+ }
+}
+
+static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
+{
+ PCIIDEState *d = opaque;
+ int ret, i;
+
+ if (version_id != 2 && version_id != 3)
+ return -EINVAL;
+ ret = pci_device_load(&d->dev, f);
+ if (ret < 0)
+ return ret;
+
+ for(i = 0; i < 2; i++) {
+ BMDMAState *bm = &d->bmdma[i];
+ uint8_t ifidx;
+ qemu_get_8s(f, &bm->cmd);
+ qemu_get_8s(f, &bm->status);
+ qemu_get_be32s(f, &bm->addr);
+ qemu_get_sbe64s(f, &bm->sector_num);
+ qemu_get_be32s(f, &bm->nsector);
+ qemu_get_8s(f, &ifidx);
+ bm->unit = ifidx & 1;
+ /* XXX: if a transfer is pending, we do not save it yet */
+ }
+
+ /* per IDE interface data */
+ for(i = 0; i < 2; i++) {
+ idebus_load(f, &d->bus[i], version_id);
+ }
+
+ /* per IDE drive data */
+ for(i = 0; i < 2; i++) {
+ ide_load(f, &d->bus[i].ifs[0], version_id);
+ ide_load(f, &d->bus[i].ifs[1], version_id);
+ }
+ return 0;
+}
+
+/* XXX: call it also when the MRDMODE is changed from the PCI config
+ registers */
+static void cmd646_update_irq(PCIIDEState *d)
+{
+ int pci_level;
+ pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
+ !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
+ ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
+ !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
+ qemu_set_irq(d->dev.irq[0], pci_level);
+}
+
+/* the PCI irq level is the logical OR of the two channels */
+static void cmd646_set_irq(void *opaque, int channel, int level)
+{
+ PCIIDEState *d = opaque;
+ int irq_mask;
+
+ irq_mask = MRDMODE_INTR_CH0 << channel;
+ if (level)
+ d->dev.config[MRDMODE] |= irq_mask;
+ else
+ d->dev.config[MRDMODE] &= ~irq_mask;
+ cmd646_update_irq(d);
+}
+
+static void cmd646_reset(void *opaque)
+{
+ PCIIDEState *d = opaque;
+ unsigned int i;
+
+ for (i = 0; i < 2; i++)
+ ide_dma_cancel(&d->bmdma[i]);
+}
+
+/* CMD646 PCI IDE controller */
+void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
+ int secondary_ide_enabled)
+{
+ PCIIDEState *d;
+ uint8_t *pci_conf;
+ qemu_irq *irq;
+
+ d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
+ sizeof(PCIIDEState),
+ -1,
+ NULL, NULL);
+ d->type = IDE_TYPE_CMD646;
+ pci_conf = d->dev.config;
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD);
+ pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646);
+
+ pci_conf[0x08] = 0x07; // IDE controller revision
+ pci_conf[0x09] = 0x8f;
+
+ pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
+ pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
+
+ pci_conf[0x51] = 0x04; // enable IDE0
+ if (secondary_ide_enabled) {
+ /* XXX: if not enabled, really disable the seconday IDE controller */
+ pci_conf[0x51] |= 0x08; /* enable IDE1 */
+ }
+
+ pci_register_bar((PCIDevice *)d, 0, 0x8,
+ PCI_ADDRESS_SPACE_IO, ide_map);
+ pci_register_bar((PCIDevice *)d, 1, 0x4,
+ PCI_ADDRESS_SPACE_IO, ide_map);
+ pci_register_bar((PCIDevice *)d, 2, 0x8,
+ PCI_ADDRESS_SPACE_IO, ide_map);
+ pci_register_bar((PCIDevice *)d, 3, 0x4,
+ PCI_ADDRESS_SPACE_IO, ide_map);
+ pci_register_bar((PCIDevice *)d, 4, 0x10,
+ PCI_ADDRESS_SPACE_IO, bmdma_map);
+
+ pci_conf[0x3d] = 0x01; // interrupt on pin 1
+
+ irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
+ ide_init2(&d->bus[0], hd_table[0], hd_table[1], irq[0]);
+ ide_init2(&d->bus[1], hd_table[2], hd_table[3], irq[1]);
+
+ register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
+ qemu_register_reset(cmd646_reset, d);
+ cmd646_reset(d);
+}
+
+static void piix3_reset(void *opaque)
+{
+ PCIIDEState *d = opaque;
+ uint8_t *pci_conf = d->dev.config;
+ int i;
+
+ for (i = 0; i < 2; i++)
+ ide_dma_cancel(&d->bmdma[i]);
+
+ pci_conf[0x04] = 0x00;
+ pci_conf[0x05] = 0x00;
+ pci_conf[0x06] = 0x80; /* FBC */
+ pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
+ pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
+}
+
+/* hd_table must contain 4 block drivers */
+/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
+void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
+ qemu_irq *pic)
+{
+ PCIIDEState *d;
+ uint8_t *pci_conf;
+ int i;
+
+ /* register a function 1 of PIIX3 */
+ d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
+ sizeof(PCIIDEState),
+ devfn,
+ NULL, NULL);
+ d->type = IDE_TYPE_PIIX3;
+
+ pci_conf = d->dev.config;
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_1);
+ pci_conf[0x09] = 0x80; // legacy ATA mode
+ pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
+ pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
+
+ qemu_register_reset(piix3_reset, d);
+ piix3_reset(d);
+
+ pci_register_bar((PCIDevice *)d, 4, 0x10,
+ PCI_ADDRESS_SPACE_IO, bmdma_map);
+
+ ide_init2(&d->bus[0], hd_table[0], hd_table[1], pic[14]);
+ ide_init2(&d->bus[1], hd_table[2], hd_table[3], pic[15]);
+ ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
+ ide_init_ioport(&d->bus[1], 0x170, 0x376);
+
+ for (i = 0; i < 4; i++)
+ if (hd_table[i])
+ hd_table[i]->private = &d->dev;
+
+ register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
+}
+
+/* hd_table must contain 4 block drivers */
+/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
+void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
+ qemu_irq *pic)
+{
+ PCIIDEState *d;
+ uint8_t *pci_conf;
+
+ /* register a function 1 of PIIX4 */
+ d = (PCIIDEState *)pci_register_device(bus, "PIIX4 IDE",
+ sizeof(PCIIDEState),
+ devfn,
+ NULL, NULL);
+ d->type = IDE_TYPE_PIIX4;
+
+ pci_conf = d->dev.config;
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB);
+ pci_conf[0x09] = 0x80; // legacy ATA mode
+ pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
+ pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
+
+ qemu_register_reset(piix3_reset, d);
+ piix3_reset(d);
+
+ pci_register_bar((PCIDevice *)d, 4, 0x10,
+ PCI_ADDRESS_SPACE_IO, bmdma_map);
+
+ ide_init2(&d->bus[0], hd_table[0], hd_table[1], pic[14]);
+ ide_init2(&d->bus[1], hd_table[2], hd_table[3], pic[15]);
+ ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
+ ide_init_ioport(&d->bus[1], 0x170, 0x376);
+
+ register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
+}
+
diff --git a/hw/ide.c b/hw/ide.c
index 5fb42b7..c68df00 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -389,63 +389,6 @@ static inline int media_is_cd(IDEState *s)
return (media_present(s) && s->nb_sectors <= CD_MAX_SECTORS);
}
-#define BM_STATUS_DMAING 0x01
-#define BM_STATUS_ERROR 0x02
-#define BM_STATUS_INT 0x04
-#define BM_STATUS_DMA_RETRY 0x08
-#define BM_STATUS_PIO_RETRY 0x10
-
-#define BM_CMD_START 0x01
-#define BM_CMD_READ 0x08
-
-#define IDE_TYPE_PIIX3 0
-#define IDE_TYPE_CMD646 1
-#define IDE_TYPE_PIIX4 2
-
-/* CMD646 specific */
-#define MRDMODE 0x71
-#define MRDMODE_INTR_CH0 0x04
-#define MRDMODE_INTR_CH1 0x08
-#define MRDMODE_BLK_CH0 0x10
-#define MRDMODE_BLK_CH1 0x20
-#define UDIDETCR0 0x73
-#define UDIDETCR1 0x7B
-
-struct BMDMAState {
- uint8_t cmd;
- uint8_t status;
- uint32_t addr;
-
- struct PCIIDEState *pci_dev;
- IDEBus *bus;
- /* current transfer state */
- uint32_t cur_addr;
- uint32_t cur_prd_last;
- uint32_t cur_prd_addr;
- uint32_t cur_prd_len;
- uint8_t unit;
- BlockDriverCompletionFunc *dma_cb;
- BlockDriverAIOCB *aiocb;
- struct iovec iov;
- QEMUIOVector qiov;
- int64_t sector_num;
- uint32_t nsector;
- QEMUBH *bh;
-};
-
-typedef struct PCIIDEState {
- PCIDevice dev;
- IDEBus bus[2];
- BMDMAState bmdma[2];
- int type; /* see IDE_TYPE_xxx */
-} PCIIDEState;
-
-static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
-{
- assert(bmdma->unit != -1);
- return bmdma->bus->ifs + bmdma->unit;
-}
-
static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb);
static void ide_dma_restart(IDEState *s);
static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret);
@@ -1061,7 +1004,7 @@ static void ide_dma_restart_bh(void *opaque)
}
}
-static void ide_dma_restart_cb(void *opaque, int running, int reason)
+void ide_dma_restart_cb(void *opaque, int running, int reason)
{
BMDMAState *bm = opaque;
@@ -2092,7 +2035,7 @@ static void ide_clear_hob(IDEBus *bus)
bus->ifs[1].select &= ~(1 << 7);
}
-static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s;
@@ -2508,7 +2451,7 @@ static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
}
}
-static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
+uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
@@ -2586,7 +2529,7 @@ static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
return ret;
}
-static uint32_t ide_status_read(void *opaque, uint32_t addr)
+uint32_t ide_status_read(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
@@ -2603,7 +2546,7 @@ static uint32_t ide_status_read(void *opaque, uint32_t addr)
return ret;
}
-static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
+void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s;
@@ -2638,7 +2581,7 @@ static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
bus->ifs[1].cmd = val;
}
-static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
+void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
@@ -2656,7 +2599,7 @@ static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
s->end_transfer_func(s);
}
-static uint32_t ide_data_readw(void *opaque, uint32_t addr)
+uint32_t ide_data_readw(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
@@ -2676,7 +2619,7 @@ static uint32_t ide_data_readw(void *opaque, uint32_t addr)
return ret;
}
-static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
+void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
@@ -2694,7 +2637,7 @@ static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
s->end_transfer_func(s);
}
-static uint32_t ide_data_readl(void *opaque, uint32_t addr)
+uint32_t ide_data_readl(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
@@ -2884,32 +2827,6 @@ void idebus_load(QEMUFile* f, IDEBus *bus, int version_id)
/***********************************************************/
/* PCI IDE definitions */
-static void cmd646_update_irq(PCIIDEState *d);
-
-static void ide_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
-{
- PCIIDEState *d = (PCIIDEState *)pci_dev;
- IDEBus *bus;
-
- if (region_num <= 3) {
- bus = &d->bus[(region_num >> 1)];
- if (region_num & 1) {
- register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
- register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
- } else {
- register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
- register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
-
- /* data ports */
- register_ioport_write(addr, 2, 2, ide_data_writew, bus);
- register_ioport_read(addr, 2, 2, ide_data_readw, bus);
- register_ioport_write(addr, 4, 4, ide_data_writel, bus);
- register_ioport_read(addr, 4, 4, ide_data_readl, bus);
- }
- }
-}
-
static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb)
{
BMDMAState *bm = s->bus->bmdma;
@@ -2939,7 +2856,7 @@ static void ide_dma_restart(IDEState *s)
ide_dma_start(s, bm->dma_cb);
}
-static void ide_dma_cancel(BMDMAState *bm)
+void ide_dma_cancel(BMDMAState *bm)
{
if (bm->status & BM_STATUS_DMAING) {
bm->status &= ~BM_STATUS_DMAING;
@@ -2956,443 +2873,6 @@ static void ide_dma_cancel(BMDMAState *bm)
}
}
-static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
-{
- BMDMAState *bm = opaque;
-#ifdef DEBUG_IDE
- printf("%s: 0x%08x\n", __func__, val);
-#endif
- if (!(val & BM_CMD_START)) {
- /* XXX: do it better */
- ide_dma_cancel(bm);
- bm->cmd = val & 0x09;
- } else {
- if (!(bm->status & BM_STATUS_DMAING)) {
- bm->status |= BM_STATUS_DMAING;
- /* start dma transfer if possible */
- if (bm->dma_cb)
- bm->dma_cb(bm, 0);
- }
- bm->cmd = val & 0x09;
- }
-}
-
-static uint32_t bmdma_readb(void *opaque, uint32_t addr)
-{
- BMDMAState *bm = opaque;
- PCIIDEState *pci_dev;
- uint32_t val;
-
- switch(addr & 3) {
- case 0:
- val = bm->cmd;
- break;
- case 1:
- pci_dev = bm->pci_dev;
- if (pci_dev->type == IDE_TYPE_CMD646) {
- val = pci_dev->dev.config[MRDMODE];
- } else {
- val = 0xff;
- }
- break;
- case 2:
- val = bm->status;
- break;
- case 3:
- pci_dev = bm->pci_dev;
- if (pci_dev->type == IDE_TYPE_CMD646) {
- if (bm == &pci_dev->bmdma[0])
- val = pci_dev->dev.config[UDIDETCR0];
- else
- val = pci_dev->dev.config[UDIDETCR1];
- } else {
- val = 0xff;
- }
- break;
- default:
- val = 0xff;
- break;
- }
-#ifdef DEBUG_IDE
- printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
-#endif
- return val;
-}
-
-static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
-{
- BMDMAState *bm = opaque;
- PCIIDEState *pci_dev;
-#ifdef DEBUG_IDE
- printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
-#endif
- switch(addr & 3) {
- case 1:
- pci_dev = bm->pci_dev;
- if (pci_dev->type == IDE_TYPE_CMD646) {
- pci_dev->dev.config[MRDMODE] =
- (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
- cmd646_update_irq(pci_dev);
- }
- break;
- case 2:
- bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
- break;
- case 3:
- pci_dev = bm->pci_dev;
- if (pci_dev->type == IDE_TYPE_CMD646) {
- if (bm == &pci_dev->bmdma[0])
- pci_dev->dev.config[UDIDETCR0] = val;
- else
- pci_dev->dev.config[UDIDETCR1] = val;
- }
- break;
- }
-}
-
-static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr)
-{
- BMDMAState *bm = opaque;
- uint32_t val;
- val = (bm->addr >> ((addr & 3) * 8)) & 0xff;
-#ifdef DEBUG_IDE
- printf("%s: 0x%08x\n", __func__, val);
-#endif
- return val;
-}
-
-static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val)
-{
- BMDMAState *bm = opaque;
- int shift = (addr & 3) * 8;
-#ifdef DEBUG_IDE
- printf("%s: 0x%08x\n", __func__, val);
-#endif
- bm->addr &= ~(0xFF << shift);
- bm->addr |= ((val & 0xFF) << shift) & ~3;
- bm->cur_addr = bm->addr;
-}
-
-static uint32_t bmdma_addr_readw(void *opaque, uint32_t addr)
-{
- BMDMAState *bm = opaque;
- uint32_t val;
- val = (bm->addr >> ((addr & 3) * 8)) & 0xffff;
-#ifdef DEBUG_IDE
- printf("%s: 0x%08x\n", __func__, val);
-#endif
- return val;
-}
-
-static void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val)
-{
- BMDMAState *bm = opaque;
- int shift = (addr & 3) * 8;
-#ifdef DEBUG_IDE
- printf("%s: 0x%08x\n", __func__, val);
-#endif
- bm->addr &= ~(0xFFFF << shift);
- bm->addr |= ((val & 0xFFFF) << shift) & ~3;
- bm->cur_addr = bm->addr;
-}
-
-static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
-{
- BMDMAState *bm = opaque;
- uint32_t val;
- val = bm->addr;
-#ifdef DEBUG_IDE
- printf("%s: 0x%08x\n", __func__, val);
-#endif
- return val;
-}
-
-static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
-{
- BMDMAState *bm = opaque;
-#ifdef DEBUG_IDE
- printf("%s: 0x%08x\n", __func__, val);
-#endif
- bm->addr = val & ~3;
- bm->cur_addr = bm->addr;
-}
-
-static void bmdma_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
-{
- PCIIDEState *d = (PCIIDEState *)pci_dev;
- int i;
-
- for(i = 0;i < 2; i++) {
- BMDMAState *bm = &d->bmdma[i];
- d->bus[i].bmdma = bm;
- bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev);
- bm->bus = d->bus+i;
- qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
-
- register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
-
- register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
- register_ioport_read(addr, 4, 1, bmdma_readb, bm);
-
- register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
- register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
- register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
- register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
- register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
- register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
- addr += 8;
- }
-}
-
-static void pci_ide_save(QEMUFile* f, void *opaque)
-{
- PCIIDEState *d = opaque;
- int i;
-
- pci_device_save(&d->dev, f);
-
- for(i = 0; i < 2; i++) {
- BMDMAState *bm = &d->bmdma[i];
- uint8_t ifidx;
- qemu_put_8s(f, &bm->cmd);
- qemu_put_8s(f, &bm->status);
- qemu_put_be32s(f, &bm->addr);
- qemu_put_sbe64s(f, &bm->sector_num);
- qemu_put_be32s(f, &bm->nsector);
- ifidx = bm->unit + 2*i;
- qemu_put_8s(f, &ifidx);
- /* XXX: if a transfer is pending, we do not save it yet */
- }
-
- /* per IDE interface data */
- for(i = 0; i < 2; i++) {
- idebus_save(f, &d->bus[i]);
- }
-
- /* per IDE drive data */
- for(i = 0; i < 2; i++) {
- ide_save(f, &d->bus[i].ifs[0]);
- ide_save(f, &d->bus[i].ifs[1]);
- }
-}
-
-static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
-{
- PCIIDEState *d = opaque;
- int ret, i;
-
- if (version_id != 2 && version_id != 3)
- return -EINVAL;
- ret = pci_device_load(&d->dev, f);
- if (ret < 0)
- return ret;
-
- for(i = 0; i < 2; i++) {
- BMDMAState *bm = &d->bmdma[i];
- uint8_t ifidx;
- qemu_get_8s(f, &bm->cmd);
- qemu_get_8s(f, &bm->status);
- qemu_get_be32s(f, &bm->addr);
- qemu_get_sbe64s(f, &bm->sector_num);
- qemu_get_be32s(f, &bm->nsector);
- qemu_get_8s(f, &ifidx);
- bm->unit = ifidx & 1;
- /* XXX: if a transfer is pending, we do not save it yet */
- }
-
- /* per IDE interface data */
- for(i = 0; i < 2; i++) {
- idebus_load(f, &d->bus[i], version_id);
- }
-
- /* per IDE drive data */
- for(i = 0; i < 2; i++) {
- ide_load(f, &d->bus[i].ifs[0], version_id);
- ide_load(f, &d->bus[i].ifs[1], version_id);
- }
- return 0;
-}
-
-/* XXX: call it also when the MRDMODE is changed from the PCI config
- registers */
-static void cmd646_update_irq(PCIIDEState *d)
-{
- int pci_level;
- pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
- !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
- ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
- !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
- qemu_set_irq(d->dev.irq[0], pci_level);
-}
-
-/* the PCI irq level is the logical OR of the two channels */
-static void cmd646_set_irq(void *opaque, int channel, int level)
-{
- PCIIDEState *d = opaque;
- int irq_mask;
-
- irq_mask = MRDMODE_INTR_CH0 << channel;
- if (level)
- d->dev.config[MRDMODE] |= irq_mask;
- else
- d->dev.config[MRDMODE] &= ~irq_mask;
- cmd646_update_irq(d);
-}
-
-static void cmd646_reset(void *opaque)
-{
- PCIIDEState *d = opaque;
- unsigned int i;
-
- for (i = 0; i < 2; i++)
- ide_dma_cancel(&d->bmdma[i]);
-}
-
-/* CMD646 PCI IDE controller */
-void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
- int secondary_ide_enabled)
-{
- PCIIDEState *d;
- uint8_t *pci_conf;
- qemu_irq *irq;
-
- d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
- sizeof(PCIIDEState),
- -1,
- NULL, NULL);
- d->type = IDE_TYPE_CMD646;
- pci_conf = d->dev.config;
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646);
-
- pci_conf[0x08] = 0x07; // IDE controller revision
- pci_conf[0x09] = 0x8f;
-
- pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
- pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
-
- pci_conf[0x51] = 0x04; // enable IDE0
- if (secondary_ide_enabled) {
- /* XXX: if not enabled, really disable the seconday IDE controller */
- pci_conf[0x51] |= 0x08; /* enable IDE1 */
- }
-
- pci_register_bar((PCIDevice *)d, 0, 0x8,
- PCI_ADDRESS_SPACE_IO, ide_map);
- pci_register_bar((PCIDevice *)d, 1, 0x4,
- PCI_ADDRESS_SPACE_IO, ide_map);
- pci_register_bar((PCIDevice *)d, 2, 0x8,
- PCI_ADDRESS_SPACE_IO, ide_map);
- pci_register_bar((PCIDevice *)d, 3, 0x4,
- PCI_ADDRESS_SPACE_IO, ide_map);
- pci_register_bar((PCIDevice *)d, 4, 0x10,
- PCI_ADDRESS_SPACE_IO, bmdma_map);
-
- pci_conf[0x3d] = 0x01; // interrupt on pin 1
-
- irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
- ide_init2(&d->bus[0], hd_table[0], hd_table[1], irq[0]);
- ide_init2(&d->bus[1], hd_table[2], hd_table[3], irq[1]);
-
- register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
- qemu_register_reset(cmd646_reset, d);
- cmd646_reset(d);
-}
-
-static void piix3_reset(void *opaque)
-{
- PCIIDEState *d = opaque;
- uint8_t *pci_conf = d->dev.config;
- int i;
-
- for (i = 0; i < 2; i++)
- ide_dma_cancel(&d->bmdma[i]);
-
- pci_conf[0x04] = 0x00;
- pci_conf[0x05] = 0x00;
- pci_conf[0x06] = 0x80; /* FBC */
- pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
- pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
-}
-
-/* hd_table must contain 4 block drivers */
-/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
-void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
- qemu_irq *pic)
-{
- PCIIDEState *d;
- uint8_t *pci_conf;
- int i;
-
- /* register a function 1 of PIIX3 */
- d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
- sizeof(PCIIDEState),
- devfn,
- NULL, NULL);
- d->type = IDE_TYPE_PIIX3;
-
- pci_conf = d->dev.config;
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_1);
- pci_conf[0x09] = 0x80; // legacy ATA mode
- pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
- pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
-
- qemu_register_reset(piix3_reset, d);
- piix3_reset(d);
-
- pci_register_bar((PCIDevice *)d, 4, 0x10,
- PCI_ADDRESS_SPACE_IO, bmdma_map);
-
- ide_init2(&d->bus[0], hd_table[0], hd_table[1], pic[14]);
- ide_init2(&d->bus[1], hd_table[2], hd_table[3], pic[15]);
- ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
- ide_init_ioport(&d->bus[1], 0x170, 0x376);
-
- for (i = 0; i < 4; i++)
- if (hd_table[i])
- hd_table[i]->private = &d->dev;
-
- register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
-}
-
-/* hd_table must contain 4 block drivers */
-/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
-void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
- qemu_irq *pic)
-{
- PCIIDEState *d;
- uint8_t *pci_conf;
-
- /* register a function 1 of PIIX4 */
- d = (PCIIDEState *)pci_register_device(bus, "PIIX4 IDE",
- sizeof(PCIIDEState),
- devfn,
- NULL, NULL);
- d->type = IDE_TYPE_PIIX4;
-
- pci_conf = d->dev.config;
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB);
- pci_conf[0x09] = 0x80; // legacy ATA mode
- pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
- pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
-
- qemu_register_reset(piix3_reset, d);
- piix3_reset(d);
-
- pci_register_bar((PCIDevice *)d, 4, 0x10,
- PCI_ADDRESS_SPACE_IO, bmdma_map);
-
- ide_init2(&d->bus[0], hd_table[0], hd_table[1], pic[14]);
- ide_init2(&d->bus[1], hd_table[2], hd_table[3], pic[15]);
- ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
- ide_init_ioport(&d->bus[1], 0x170, 0x376);
-
- register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
-}
-
#if defined(TARGET_PPC)
/***********************************************************/
/* MacIO based PowerPC IDE */
diff --git a/hw/ide.h b/hw/ide.h
index 73ef93e..faa04a3 100644
--- a/hw/ide.h
+++ b/hw/ide.h
@@ -7,4 +7,12 @@
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
BlockDriverState *hd0, BlockDriverState *hd1);
+/* ide-pci.c */
+void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
+ int secondary_ide_enabled);
+void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
+ qemu_irq *pic);
+void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
+ qemu_irq *pic);
+
#endif /* HW_IDE_H */
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 4e51c8d..1927e4b 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -38,6 +38,7 @@
#include "boards.h"
#include "qemu-log.h"
#include "mips-bios.h"
+#include "ide.h"
//#define DEBUG_BOARD_INIT
diff --git a/hw/pc.h b/hw/pc.h
index a8b593f..3b34213 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -151,14 +151,6 @@ int isa_vga_mm_init(target_phys_addr_t vram_base,
void pci_cirrus_vga_init(PCIBus *bus);
void isa_cirrus_vga_init(void);
-/* ide.c */
-void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
- int secondary_ide_enabled);
-void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
- qemu_irq *pic);
-void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
- qemu_irq *pic);
-
/* ne2000.c */
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index 784e527..c388be9 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -35,6 +35,7 @@
#include "fw_cfg.h"
#include "escc.h"
#include "openpic.h"
+#include "ide.h"
#define MAX_IDE_BUS 2
#define VGA_BIOS_SIZE 65536
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index 549ba0c..4ff6a33 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -35,6 +35,7 @@
#include "boards.h"
#include "fw_cfg.h"
#include "escc.h"
+#include "ide.h"
#define MAX_IDE_BUS 2
#define VGA_BIOS_SIZE 65536
diff --git a/hw/sun4u.c b/hw/sun4u.c
index bc83255..8e66301 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -33,6 +33,7 @@
#include "firmware_abi.h"
#include "fw_cfg.h"
#include "sysbus.h"
+#include "ide.h"
//#define DEBUG_IRQ
--
1.6.2.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Qemu-devel] [PATCH 5/8] ide: split away ide-macio.c
2009-08-18 16:06 [Qemu-devel] [PATCH 0/8] ide: cleanup and splitting Gerd Hoffmann
` (3 preceding siblings ...)
2009-08-18 16:06 ` [Qemu-devel] [PATCH 4/8] ide: split away ide-pci.c Gerd Hoffmann
@ 2009-08-18 16:06 ` Gerd Hoffmann
[not found] ` <m34os4qfv2.fsf@neno.mitica>
2009-08-18 16:06 ` [Qemu-devel] [PATCH 6/8] ide: split away ide-mmio.c Gerd Hoffmann
` (3 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Gerd Hoffmann @ 2009-08-18 16:06 UTC (permalink / raw)
To: qemu-devel; +Cc: Gerd Hoffmann
create ide-macio.c and place macio support there.
only build ide-macio support for platforms using it.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
Makefile.target | 2 +-
hw/ide-internal.h | 356 +++++++++++++++++++++++++++
hw/ide-macio.c | 355 +++++++++++++++++++++++++++
hw/ide.c | 688 +----------------------------------------------------
hw/ide.h | 4 +
hw/ppc_mac.h | 4 -
6 files changed, 723 insertions(+), 686 deletions(-)
create mode 100644 hw/ide-macio.c
diff --git a/Makefile.target b/Makefile.target
index fbc76d4..08afa82 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -190,7 +190,7 @@ obj-i386-y += usb-uhci.o vmmouse.o vmport.o vmware_vga.o hpet.o
obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o
# shared objects
-obj-ppc-y = ppc.o ide.o ide-isa.o ide-pci.o
+obj-ppc-y = ppc.o ide.o ide-isa.o ide-pci.o ide-macio.o
obj-ppc-y += vga.o $(sound-obj-y) dma.o isa-bus.o openpic.o
# PREP target
obj-ppc-y += pckbd.o serial.o i8259.o i8254.o fdc.o mc146818rtc.o
diff --git a/hw/ide-internal.h b/hw/ide-internal.h
index 47e92cf..80dab28 100644
--- a/hw/ide-internal.h
+++ b/hw/ide-internal.h
@@ -3,12 +3,348 @@
#include "ide.h"
+/* debug IDE devices */
+//#define DEBUG_IDE
+//#define DEBUG_IDE_ATAPI
+//#define DEBUG_AIO
+#define USE_DMA_CDROM
+
typedef struct IDEBus IDEBus;
typedef struct IDEState IDEState;
typedef struct BMDMAState BMDMAState;
typedef void EndTransferFunc(IDEState *);
+/* Bits of HD_STATUS */
+#define ERR_STAT 0x01
+#define INDEX_STAT 0x02
+#define ECC_STAT 0x04 /* Corrected error */
+#define DRQ_STAT 0x08
+#define SEEK_STAT 0x10
+#define SRV_STAT 0x10
+#define WRERR_STAT 0x20
+#define READY_STAT 0x40
+#define BUSY_STAT 0x80
+
+/* Bits for HD_ERROR */
+#define MARK_ERR 0x01 /* Bad address mark */
+#define TRK0_ERR 0x02 /* couldn't find track 0 */
+#define ABRT_ERR 0x04 /* Command aborted */
+#define MCR_ERR 0x08 /* media change request */
+#define ID_ERR 0x10 /* ID field not found */
+#define MC_ERR 0x20 /* media changed */
+#define ECC_ERR 0x40 /* Uncorrectable ECC error */
+#define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
+#define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
+
+/* Bits of HD_NSECTOR */
+#define CD 0x01
+#define IO 0x02
+#define REL 0x04
+#define TAG_MASK 0xf8
+
+#define IDE_CMD_RESET 0x04
+#define IDE_CMD_DISABLE_IRQ 0x02
+
+/* ATA/ATAPI Commands pre T13 Spec */
+#define WIN_NOP 0x00
+/*
+ * 0x01->0x02 Reserved
+ */
+#define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
+/*
+ * 0x04->0x07 Reserved
+ */
+#define WIN_SRST 0x08 /* ATAPI soft reset command */
+#define WIN_DEVICE_RESET 0x08
+/*
+ * 0x09->0x0F Reserved
+ */
+#define WIN_RECAL 0x10
+#define WIN_RESTORE WIN_RECAL
+/*
+ * 0x10->0x1F Reserved
+ */
+#define WIN_READ 0x20 /* 28-Bit */
+#define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
+#define WIN_READ_LONG 0x22 /* 28-Bit */
+#define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
+#define WIN_READ_EXT 0x24 /* 48-Bit */
+#define WIN_READDMA_EXT 0x25 /* 48-Bit */
+#define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
+#define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
+/*
+ * 0x28
+ */
+#define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
+/*
+ * 0x2A->0x2F Reserved
+ */
+#define WIN_WRITE 0x30 /* 28-Bit */
+#define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
+#define WIN_WRITE_LONG 0x32 /* 28-Bit */
+#define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
+#define WIN_WRITE_EXT 0x34 /* 48-Bit */
+#define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
+#define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
+#define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
+#define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
+#define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
+/*
+ * 0x3A->0x3B Reserved
+ */
+#define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
+/*
+ * 0x3D->0x3F Reserved
+ */
+#define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
+#define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
+#define WIN_VERIFY_EXT 0x42 /* 48-Bit */
+/*
+ * 0x43->0x4F Reserved
+ */
+#define WIN_FORMAT 0x50
+/*
+ * 0x51->0x5F Reserved
+ */
+#define WIN_INIT 0x60
+/*
+ * 0x61->0x5F Reserved
+ */
+#define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
+#define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
+#define WIN_DIAGNOSE 0x90
+#define WIN_SPECIFY 0x91 /* set drive geometry translation */
+#define WIN_DOWNLOAD_MICROCODE 0x92
+#define WIN_STANDBYNOW2 0x94
+#define CFA_IDLEIMMEDIATE 0x95 /* force drive to become "ready" */
+#define WIN_STANDBY2 0x96
+#define WIN_SETIDLE2 0x97
+#define WIN_CHECKPOWERMODE2 0x98
+#define WIN_SLEEPNOW2 0x99
+/*
+ * 0x9A VENDOR
+ */
+#define WIN_PACKETCMD 0xA0 /* Send a packet command. */
+#define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
+#define WIN_QUEUED_SERVICE 0xA2
+#define WIN_SMART 0xB0 /* self-monitoring and reporting */
+#define CFA_ACCESS_METADATA_STORAGE 0xB8
+#define CFA_ERASE_SECTORS 0xC0 /* microdrives implement as NOP */
+#define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
+#define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
+#define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
+#define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
+#define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
+#define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
+#define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
+#define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
+#define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
+#define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
+#define WIN_GETMEDIASTATUS 0xDA
+#define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
+#define WIN_POSTBOOT 0xDC
+#define WIN_PREBOOT 0xDD
+#define WIN_DOORLOCK 0xDE /* lock door on removable drives */
+#define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
+#define WIN_STANDBYNOW1 0xE0
+#define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
+#define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
+#define WIN_SETIDLE1 0xE3
+#define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
+#define WIN_CHECKPOWERMODE1 0xE5
+#define WIN_SLEEPNOW1 0xE6
+#define WIN_FLUSH_CACHE 0xE7
+#define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
+#define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
+ /* SET_FEATURES 0x22 or 0xDD */
+#define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
+#define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
+#define WIN_MEDIAEJECT 0xED
+#define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
+#define WIN_SETFEATURES 0xEF /* set special drive features */
+#define EXABYTE_ENABLE_NEST 0xF0
+#define IBM_SENSE_CONDITION 0xF0 /* measure disk temperature */
+#define WIN_SECURITY_SET_PASS 0xF1
+#define WIN_SECURITY_UNLOCK 0xF2
+#define WIN_SECURITY_ERASE_PREPARE 0xF3
+#define WIN_SECURITY_ERASE_UNIT 0xF4
+#define WIN_SECURITY_FREEZE_LOCK 0xF5
+#define CFA_WEAR_LEVEL 0xF5 /* microdrives implement as NOP */
+#define WIN_SECURITY_DISABLE 0xF6
+#define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
+#define WIN_SET_MAX 0xF9
+#define DISABLE_SEAGATE 0xFB
+
+/* set to 1 set disable mult support */
+#define MAX_MULT_SECTORS 16
+
+#define IDE_DMA_BUF_SECTORS 256
+
+#if (IDE_DMA_BUF_SECTORS < MAX_MULT_SECTORS)
+#error "IDE_DMA_BUF_SECTORS must be bigger or equal to MAX_MULT_SECTORS"
+#endif
+
+/* ATAPI defines */
+
+#define ATAPI_PACKET_SIZE 12
+
+/* The generic packet command opcodes for CD/DVD Logical Units,
+ * From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
+#define GPCMD_BLANK 0xa1
+#define GPCMD_CLOSE_TRACK 0x5b
+#define GPCMD_FLUSH_CACHE 0x35
+#define GPCMD_FORMAT_UNIT 0x04
+#define GPCMD_GET_CONFIGURATION 0x46
+#define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a
+#define GPCMD_GET_PERFORMANCE 0xac
+#define GPCMD_INQUIRY 0x12
+#define GPCMD_LOAD_UNLOAD 0xa6
+#define GPCMD_MECHANISM_STATUS 0xbd
+#define GPCMD_MODE_SELECT_10 0x55
+#define GPCMD_MODE_SENSE_10 0x5a
+#define GPCMD_PAUSE_RESUME 0x4b
+#define GPCMD_PLAY_AUDIO_10 0x45
+#define GPCMD_PLAY_AUDIO_MSF 0x47
+#define GPCMD_PLAY_AUDIO_TI 0x48
+#define GPCMD_PLAY_CD 0xbc
+#define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1e
+#define GPCMD_READ_10 0x28
+#define GPCMD_READ_12 0xa8
+#define GPCMD_READ_CDVD_CAPACITY 0x25
+#define GPCMD_READ_CD 0xbe
+#define GPCMD_READ_CD_MSF 0xb9
+#define GPCMD_READ_DISC_INFO 0x51
+#define GPCMD_READ_DVD_STRUCTURE 0xad
+#define GPCMD_READ_FORMAT_CAPACITIES 0x23
+#define GPCMD_READ_HEADER 0x44
+#define GPCMD_READ_TRACK_RZONE_INFO 0x52
+#define GPCMD_READ_SUBCHANNEL 0x42
+#define GPCMD_READ_TOC_PMA_ATIP 0x43
+#define GPCMD_REPAIR_RZONE_TRACK 0x58
+#define GPCMD_REPORT_KEY 0xa4
+#define GPCMD_REQUEST_SENSE 0x03
+#define GPCMD_RESERVE_RZONE_TRACK 0x53
+#define GPCMD_SCAN 0xba
+#define GPCMD_SEEK 0x2b
+#define GPCMD_SEND_DVD_STRUCTURE 0xad
+#define GPCMD_SEND_EVENT 0xa2
+#define GPCMD_SEND_KEY 0xa3
+#define GPCMD_SEND_OPC 0x54
+#define GPCMD_SET_READ_AHEAD 0xa7
+#define GPCMD_SET_STREAMING 0xb6
+#define GPCMD_START_STOP_UNIT 0x1b
+#define GPCMD_STOP_PLAY_SCAN 0x4e
+#define GPCMD_TEST_UNIT_READY 0x00
+#define GPCMD_VERIFY_10 0x2f
+#define GPCMD_WRITE_10 0x2a
+#define GPCMD_WRITE_AND_VERIFY_10 0x2e
+/* This is listed as optional in ATAPI 2.6, but is (curiously)
+ * missing from Mt. Fuji, Table 57. It _is_ mentioned in Mt. Fuji
+ * Table 377 as an MMC command for SCSi devices though... Most ATAPI
+ * drives support it. */
+#define GPCMD_SET_SPEED 0xbb
+/* This seems to be a SCSI specific CD-ROM opcode
+ * to play data at track/index */
+#define GPCMD_PLAYAUDIO_TI 0x48
+/*
+ * From MS Media Status Notification Support Specification. For
+ * older drives only.
+ */
+#define GPCMD_GET_MEDIA_STATUS 0xda
+#define GPCMD_MODE_SENSE_6 0x1a
+
+/* Mode page codes for mode sense/set */
+#define GPMODE_R_W_ERROR_PAGE 0x01
+#define GPMODE_WRITE_PARMS_PAGE 0x05
+#define GPMODE_AUDIO_CTL_PAGE 0x0e
+#define GPMODE_POWER_PAGE 0x1a
+#define GPMODE_FAULT_FAIL_PAGE 0x1c
+#define GPMODE_TO_PROTECT_PAGE 0x1d
+#define GPMODE_CAPABILITIES_PAGE 0x2a
+#define GPMODE_ALL_PAGES 0x3f
+/* Not in Mt. Fuji, but in ATAPI 2.6 -- depricated now in favor
+ * of MODE_SENSE_POWER_PAGE */
+#define GPMODE_CDROM_PAGE 0x0d
+
+/*
+ * Based on values from <linux/cdrom.h> but extending CD_MINS
+ * to the maximum common size allowed by the Orange's Book ATIP
+ *
+ * 90 and 99 min CDs are also available but using them as the
+ * upper limit reduces the effectiveness of the heuristic to
+ * detect DVDs burned to less than 25% of their maximum capacity
+ */
+
+/* Some generally useful CD-ROM information */
+#define CD_MINS 80 /* max. minutes per CD */
+#define CD_SECS 60 /* seconds per minute */
+#define CD_FRAMES 75 /* frames per second */
+#define CD_FRAMESIZE 2048 /* bytes per frame, "cooked" mode */
+#define CD_MAX_BYTES (CD_MINS * CD_SECS * CD_FRAMES * CD_FRAMESIZE)
+#define CD_MAX_SECTORS (CD_MAX_BYTES / 512)
+
+/*
+ * The MMC values are not IDE specific and might need to be moved
+ * to a common header if they are also needed for the SCSI emulation
+ */
+
+/* Profile list from MMC-6 revision 1 table 91 */
+#define MMC_PROFILE_NONE 0x0000
+#define MMC_PROFILE_CD_ROM 0x0008
+#define MMC_PROFILE_CD_R 0x0009
+#define MMC_PROFILE_CD_RW 0x000A
+#define MMC_PROFILE_DVD_ROM 0x0010
+#define MMC_PROFILE_DVD_R_SR 0x0011
+#define MMC_PROFILE_DVD_RAM 0x0012
+#define MMC_PROFILE_DVD_RW_RO 0x0013
+#define MMC_PROFILE_DVD_RW_SR 0x0014
+#define MMC_PROFILE_DVD_R_DL_SR 0x0015
+#define MMC_PROFILE_DVD_R_DL_JR 0x0016
+#define MMC_PROFILE_DVD_RW_DL 0x0017
+#define MMC_PROFILE_DVD_DDR 0x0018
+#define MMC_PROFILE_DVD_PLUS_RW 0x001A
+#define MMC_PROFILE_DVD_PLUS_R 0x001B
+#define MMC_PROFILE_DVD_PLUS_RW_DL 0x002A
+#define MMC_PROFILE_DVD_PLUS_R_DL 0x002B
+#define MMC_PROFILE_BD_ROM 0x0040
+#define MMC_PROFILE_BD_R_SRM 0x0041
+#define MMC_PROFILE_BD_R_RRM 0x0042
+#define MMC_PROFILE_BD_RE 0x0043
+#define MMC_PROFILE_HDDVD_ROM 0x0050
+#define MMC_PROFILE_HDDVD_R 0x0051
+#define MMC_PROFILE_HDDVD_RAM 0x0052
+#define MMC_PROFILE_HDDVD_RW 0x0053
+#define MMC_PROFILE_HDDVD_R_DL 0x0058
+#define MMC_PROFILE_HDDVD_RW_DL 0x005A
+#define MMC_PROFILE_INVALID 0xFFFF
+
+#define ATAPI_INT_REASON_CD 0x01 /* 0 = data transfer */
+#define ATAPI_INT_REASON_IO 0x02 /* 1 = transfer to the host */
+#define ATAPI_INT_REASON_REL 0x04
+#define ATAPI_INT_REASON_TAG 0xf8
+
+#define CFA_NO_ERROR 0x00
+#define CFA_MISC_ERROR 0x09
+#define CFA_INVALID_COMMAND 0x20
+#define CFA_INVALID_ADDRESS 0x21
+#define CFA_ADDRESS_OVERFLOW 0x2f
+
+/* same constants as bochs */
+#define ASC_ILLEGAL_OPCODE 0x20
+#define ASC_LOGICAL_BLOCK_OOR 0x21
+#define ASC_INV_FIELD_IN_CMD_PACKET 0x24
+#define ASC_MEDIUM_MAY_HAVE_CHANGED 0x28
+#define ASC_INCOMPATIBLE_FORMAT 0x30
+#define ASC_MEDIUM_NOT_PRESENT 0x3a
+#define ASC_SAVING_PARAMETERS_NOT_SUPPORTED 0x39
+#define ASC_MEDIA_REMOVAL_PREVENTED 0x53
+
+#define SENSE_NONE 0
+#define SENSE_NOT_READY 2
+#define SENSE_ILLEGAL_REQUEST 5
+#define SENSE_UNIT_ATTENTION 6
+
/* NOTE: IDEState represents in fact one drive */
struct IDEState {
IDEBus *bus;
@@ -126,14 +462,34 @@ static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
return bmdma->bus->ifs + bmdma->unit;
}
+static inline void ide_set_irq(IDEState *s)
+{
+ BMDMAState *bm = s->bus->bmdma;
+ if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
+ if (bm) {
+ bm->status |= BM_STATUS_INT;
+ }
+ qemu_irq_raise(s->irq);
+ }
+}
+
/* ide.c */
void ide_save(QEMUFile* f, IDEState *s);
void ide_load(QEMUFile* f, IDEState *s, int version_id);
void idebus_save(QEMUFile* f, IDEBus *bus);
void idebus_load(QEMUFile* f, IDEBus *bus, int version_id);
+void ide_reset(IDEState *s);
+int64_t ide_get_sector(IDEState *s);
+void ide_set_sector(IDEState *s, int64_t sector_num);
+
void ide_dma_cancel(BMDMAState *bm);
void ide_dma_restart_cb(void *opaque, int running, int reason);
+void ide_dma_error(IDEState *s);
+
+void ide_atapi_cmd_ok(IDEState *s);
+void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc);
+void ide_atapi_io_error(IDEState *s, int ret);
void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val);
uint32_t ide_ioport_read(void *opaque, uint32_t addr1);
diff --git a/hw/ide-macio.c b/hw/ide-macio.c
new file mode 100644
index 0000000..82ed142
--- /dev/null
+++ b/hw/ide-macio.c
@@ -0,0 +1,355 @@
+/*
+ * QEMU IDE disk and CD/DVD-ROM Emulator
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2006 Openedhand Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "block.h"
+#include "block_int.h"
+#include "sysemu.h"
+#include "dma.h"
+#include "ppc_mac.h"
+#include "mac_dbdma.h"
+#include "ide-internal.h"
+
+/***********************************************************/
+/* MacIO based PowerPC IDE */
+
+typedef struct MACIOIDEState {
+ IDEBus bus;
+ BlockDriverAIOCB *aiocb;
+} MACIOIDEState;
+
+static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
+{
+ DBDMA_io *io = opaque;
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+
+ if (ret < 0) {
+ m->aiocb = NULL;
+ qemu_sglist_destroy(&s->sg);
+ ide_atapi_io_error(s, ret);
+ io->dma_end(opaque);
+ return;
+ }
+
+ if (s->io_buffer_size > 0) {
+ m->aiocb = NULL;
+ qemu_sglist_destroy(&s->sg);
+
+ s->packet_transfer_size -= s->io_buffer_size;
+
+ s->io_buffer_index += s->io_buffer_size;
+ s->lba += s->io_buffer_index >> 11;
+ s->io_buffer_index &= 0x7ff;
+ }
+
+ if (s->packet_transfer_size <= 0)
+ ide_atapi_cmd_ok(s);
+
+ if (io->len == 0) {
+ io->dma_end(opaque);
+ return;
+ }
+
+ /* launch next transfer */
+
+ s->io_buffer_size = io->len;
+
+ qemu_sglist_init(&s->sg, io->len / TARGET_PAGE_SIZE + 1);
+ qemu_sglist_add(&s->sg, io->addr, io->len);
+ io->addr += io->len;
+ io->len = 0;
+
+ m->aiocb = dma_bdrv_read(s->bs, &s->sg,
+ (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
+ pmac_ide_atapi_transfer_cb, io);
+ if (!m->aiocb) {
+ qemu_sglist_destroy(&s->sg);
+ /* Note: media not present is the most likely case */
+ ide_atapi_cmd_error(s, SENSE_NOT_READY,
+ ASC_MEDIUM_NOT_PRESENT);
+ io->dma_end(opaque);
+ return;
+ }
+}
+
+static void pmac_ide_transfer_cb(void *opaque, int ret)
+{
+ DBDMA_io *io = opaque;
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+ int n;
+ int64_t sector_num;
+
+ if (ret < 0) {
+ m->aiocb = NULL;
+ qemu_sglist_destroy(&s->sg);
+ ide_dma_error(s);
+ io->dma_end(io);
+ return;
+ }
+
+ sector_num = ide_get_sector(s);
+ if (s->io_buffer_size > 0) {
+ m->aiocb = NULL;
+ qemu_sglist_destroy(&s->sg);
+ n = (s->io_buffer_size + 0x1ff) >> 9;
+ sector_num += n;
+ ide_set_sector(s, sector_num);
+ s->nsector -= n;
+ }
+
+ /* end of transfer ? */
+ if (s->nsector == 0) {
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s);
+ }
+
+ /* end of DMA ? */
+
+ if (io->len == 0) {
+ io->dma_end(io);
+ return;
+ }
+
+ /* launch next transfer */
+
+ s->io_buffer_index = 0;
+ s->io_buffer_size = io->len;
+
+ qemu_sglist_init(&s->sg, io->len / TARGET_PAGE_SIZE + 1);
+ qemu_sglist_add(&s->sg, io->addr, io->len);
+ io->addr += io->len;
+ io->len = 0;
+
+ if (s->is_read)
+ m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
+ pmac_ide_transfer_cb, io);
+ else
+ m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
+ pmac_ide_transfer_cb, io);
+ if (!m->aiocb)
+ pmac_ide_transfer_cb(io, -1);
+}
+
+static void pmac_ide_transfer(DBDMA_io *io)
+{
+ MACIOIDEState *m = io->opaque;
+ IDEState *s = idebus_active_if(&m->bus);
+
+ s->io_buffer_size = 0;
+ if (s->is_cdrom) {
+ pmac_ide_atapi_transfer_cb(io, 0);
+ return;
+ }
+
+ pmac_ide_transfer_cb(io, 0);
+}
+
+static void pmac_ide_flush(DBDMA_io *io)
+{
+ MACIOIDEState *m = io->opaque;
+
+ if (m->aiocb)
+ qemu_aio_flush();
+}
+
+/* PowerMac IDE memory IO */
+static void pmac_ide_writeb (void *opaque,
+ target_phys_addr_t addr, uint32_t val)
+{
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ switch (addr) {
+ case 1 ... 7:
+ ide_ioport_write(&d->bus, addr, val);
+ break;
+ case 8:
+ case 22:
+ ide_cmd_write(&d->bus, 0, val);
+ break;
+ default:
+ break;
+ }
+}
+
+static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
+{
+ uint8_t retval;
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ switch (addr) {
+ case 1 ... 7:
+ retval = ide_ioport_read(&d->bus, addr);
+ break;
+ case 8:
+ case 22:
+ retval = ide_status_read(&d->bus, 0);
+ break;
+ default:
+ retval = 0xFF;
+ break;
+ }
+ return retval;
+}
+
+static void pmac_ide_writew (void *opaque,
+ target_phys_addr_t addr, uint32_t val)
+{
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+#ifdef TARGET_WORDS_BIGENDIAN
+ val = bswap16(val);
+#endif
+ if (addr == 0) {
+ ide_data_writew(&d->bus, 0, val);
+ }
+}
+
+static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
+{
+ uint16_t retval;
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ if (addr == 0) {
+ retval = ide_data_readw(&d->bus, 0);
+ } else {
+ retval = 0xFFFF;
+ }
+#ifdef TARGET_WORDS_BIGENDIAN
+ retval = bswap16(retval);
+#endif
+ return retval;
+}
+
+static void pmac_ide_writel (void *opaque,
+ target_phys_addr_t addr, uint32_t val)
+{
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+#ifdef TARGET_WORDS_BIGENDIAN
+ val = bswap32(val);
+#endif
+ if (addr == 0) {
+ ide_data_writel(&d->bus, 0, val);
+ }
+}
+
+static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
+{
+ uint32_t retval;
+ MACIOIDEState *d = opaque;
+
+ addr = (addr & 0xFFF) >> 4;
+ if (addr == 0) {
+ retval = ide_data_readl(&d->bus, 0);
+ } else {
+ retval = 0xFFFFFFFF;
+ }
+#ifdef TARGET_WORDS_BIGENDIAN
+ retval = bswap32(retval);
+#endif
+ return retval;
+}
+
+static CPUWriteMemoryFunc *pmac_ide_write[] = {
+ pmac_ide_writeb,
+ pmac_ide_writew,
+ pmac_ide_writel,
+};
+
+static CPUReadMemoryFunc *pmac_ide_read[] = {
+ pmac_ide_readb,
+ pmac_ide_readw,
+ pmac_ide_readl,
+};
+
+static void pmac_ide_save(QEMUFile *f, void *opaque)
+{
+ MACIOIDEState *d = opaque;
+ unsigned int i;
+
+ /* per IDE interface data */
+ idebus_save(f, &d->bus);
+
+ /* per IDE drive data */
+ for(i = 0; i < 2; i++) {
+ ide_save(f, &d->bus.ifs[i]);
+ }
+}
+
+static int pmac_ide_load(QEMUFile *f, void *opaque, int version_id)
+{
+ MACIOIDEState *d = opaque;
+ unsigned int i;
+
+ if (version_id != 1 && version_id != 3)
+ return -EINVAL;
+
+ /* per IDE interface data */
+ idebus_load(f, &d->bus, version_id);
+
+ /* per IDE drive data */
+ for(i = 0; i < 2; i++) {
+ ide_load(f, &d->bus.ifs[i], version_id);
+ }
+ return 0;
+}
+
+static void pmac_ide_reset(void *opaque)
+{
+ MACIOIDEState *d = opaque;
+
+ ide_reset(d->bus.ifs +0);
+ ide_reset(d->bus.ifs +1);
+}
+
+/* hd_table must contain 4 block drivers */
+/* PowerMac uses memory mapped registers, not I/O. Return the memory
+ I/O index to access the ide. */
+int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
+ void *dbdma, int channel, qemu_irq dma_irq)
+{
+ MACIOIDEState *d;
+ int pmac_ide_memory;
+
+ d = qemu_mallocz(sizeof(MACIOIDEState));
+ ide_init2(&d->bus, hd_table[0], hd_table[1], irq);
+
+ if (dbdma)
+ DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
+
+ pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
+ pmac_ide_write, d);
+ register_savevm("ide", 0, 3, pmac_ide_save, pmac_ide_load, d);
+ qemu_register_reset(pmac_ide_reset, d);
+ pmac_ide_reset(d);
+
+ return pmac_ide_memory;
+}
diff --git a/hw/ide.c b/hw/ide.c
index c68df00..d6c7dbd 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -31,348 +31,10 @@
#include "block_int.h"
#include "qemu-timer.h"
#include "sysemu.h"
-#include "ppc_mac.h"
-#include "mac_dbdma.h"
#include "sh.h"
#include "dma.h"
#include "ide-internal.h"
-/* debug IDE devices */
-//#define DEBUG_IDE
-//#define DEBUG_IDE_ATAPI
-//#define DEBUG_AIO
-#define USE_DMA_CDROM
-
-/* Bits of HD_STATUS */
-#define ERR_STAT 0x01
-#define INDEX_STAT 0x02
-#define ECC_STAT 0x04 /* Corrected error */
-#define DRQ_STAT 0x08
-#define SEEK_STAT 0x10
-#define SRV_STAT 0x10
-#define WRERR_STAT 0x20
-#define READY_STAT 0x40
-#define BUSY_STAT 0x80
-
-/* Bits for HD_ERROR */
-#define MARK_ERR 0x01 /* Bad address mark */
-#define TRK0_ERR 0x02 /* couldn't find track 0 */
-#define ABRT_ERR 0x04 /* Command aborted */
-#define MCR_ERR 0x08 /* media change request */
-#define ID_ERR 0x10 /* ID field not found */
-#define MC_ERR 0x20 /* media changed */
-#define ECC_ERR 0x40 /* Uncorrectable ECC error */
-#define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
-#define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
-
-/* Bits of HD_NSECTOR */
-#define CD 0x01
-#define IO 0x02
-#define REL 0x04
-#define TAG_MASK 0xf8
-
-#define IDE_CMD_RESET 0x04
-#define IDE_CMD_DISABLE_IRQ 0x02
-
-/* ATA/ATAPI Commands pre T13 Spec */
-#define WIN_NOP 0x00
-/*
- * 0x01->0x02 Reserved
- */
-#define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
-/*
- * 0x04->0x07 Reserved
- */
-#define WIN_SRST 0x08 /* ATAPI soft reset command */
-#define WIN_DEVICE_RESET 0x08
-/*
- * 0x09->0x0F Reserved
- */
-#define WIN_RECAL 0x10
-#define WIN_RESTORE WIN_RECAL
-/*
- * 0x10->0x1F Reserved
- */
-#define WIN_READ 0x20 /* 28-Bit */
-#define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
-#define WIN_READ_LONG 0x22 /* 28-Bit */
-#define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
-#define WIN_READ_EXT 0x24 /* 48-Bit */
-#define WIN_READDMA_EXT 0x25 /* 48-Bit */
-#define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
-#define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
-/*
- * 0x28
- */
-#define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
-/*
- * 0x2A->0x2F Reserved
- */
-#define WIN_WRITE 0x30 /* 28-Bit */
-#define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
-#define WIN_WRITE_LONG 0x32 /* 28-Bit */
-#define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
-#define WIN_WRITE_EXT 0x34 /* 48-Bit */
-#define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
-#define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
-#define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
-#define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
-#define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
-/*
- * 0x3A->0x3B Reserved
- */
-#define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
-/*
- * 0x3D->0x3F Reserved
- */
-#define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
-#define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
-#define WIN_VERIFY_EXT 0x42 /* 48-Bit */
-/*
- * 0x43->0x4F Reserved
- */
-#define WIN_FORMAT 0x50
-/*
- * 0x51->0x5F Reserved
- */
-#define WIN_INIT 0x60
-/*
- * 0x61->0x5F Reserved
- */
-#define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
-#define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
-#define WIN_DIAGNOSE 0x90
-#define WIN_SPECIFY 0x91 /* set drive geometry translation */
-#define WIN_DOWNLOAD_MICROCODE 0x92
-#define WIN_STANDBYNOW2 0x94
-#define CFA_IDLEIMMEDIATE 0x95 /* force drive to become "ready" */
-#define WIN_STANDBY2 0x96
-#define WIN_SETIDLE2 0x97
-#define WIN_CHECKPOWERMODE2 0x98
-#define WIN_SLEEPNOW2 0x99
-/*
- * 0x9A VENDOR
- */
-#define WIN_PACKETCMD 0xA0 /* Send a packet command. */
-#define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
-#define WIN_QUEUED_SERVICE 0xA2
-#define WIN_SMART 0xB0 /* self-monitoring and reporting */
-#define CFA_ACCESS_METADATA_STORAGE 0xB8
-#define CFA_ERASE_SECTORS 0xC0 /* microdrives implement as NOP */
-#define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
-#define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
-#define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
-#define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
-#define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
-#define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
-#define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
-#define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
-#define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
-#define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
-#define WIN_GETMEDIASTATUS 0xDA
-#define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
-#define WIN_POSTBOOT 0xDC
-#define WIN_PREBOOT 0xDD
-#define WIN_DOORLOCK 0xDE /* lock door on removable drives */
-#define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
-#define WIN_STANDBYNOW1 0xE0
-#define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
-#define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
-#define WIN_SETIDLE1 0xE3
-#define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
-#define WIN_CHECKPOWERMODE1 0xE5
-#define WIN_SLEEPNOW1 0xE6
-#define WIN_FLUSH_CACHE 0xE7
-#define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
-#define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
- /* SET_FEATURES 0x22 or 0xDD */
-#define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
-#define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
-#define WIN_MEDIAEJECT 0xED
-#define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
-#define WIN_SETFEATURES 0xEF /* set special drive features */
-#define EXABYTE_ENABLE_NEST 0xF0
-#define IBM_SENSE_CONDITION 0xF0 /* measure disk temperature */
-#define WIN_SECURITY_SET_PASS 0xF1
-#define WIN_SECURITY_UNLOCK 0xF2
-#define WIN_SECURITY_ERASE_PREPARE 0xF3
-#define WIN_SECURITY_ERASE_UNIT 0xF4
-#define WIN_SECURITY_FREEZE_LOCK 0xF5
-#define CFA_WEAR_LEVEL 0xF5 /* microdrives implement as NOP */
-#define WIN_SECURITY_DISABLE 0xF6
-#define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
-#define WIN_SET_MAX 0xF9
-#define DISABLE_SEAGATE 0xFB
-
-/* set to 1 set disable mult support */
-#define MAX_MULT_SECTORS 16
-
-#define IDE_DMA_BUF_SECTORS 256
-
-#if (IDE_DMA_BUF_SECTORS < MAX_MULT_SECTORS)
-#error "IDE_DMA_BUF_SECTORS must be bigger or equal to MAX_MULT_SECTORS"
-#endif
-
-/* ATAPI defines */
-
-#define ATAPI_PACKET_SIZE 12
-
-/* The generic packet command opcodes for CD/DVD Logical Units,
- * From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
-#define GPCMD_BLANK 0xa1
-#define GPCMD_CLOSE_TRACK 0x5b
-#define GPCMD_FLUSH_CACHE 0x35
-#define GPCMD_FORMAT_UNIT 0x04
-#define GPCMD_GET_CONFIGURATION 0x46
-#define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a
-#define GPCMD_GET_PERFORMANCE 0xac
-#define GPCMD_INQUIRY 0x12
-#define GPCMD_LOAD_UNLOAD 0xa6
-#define GPCMD_MECHANISM_STATUS 0xbd
-#define GPCMD_MODE_SELECT_10 0x55
-#define GPCMD_MODE_SENSE_10 0x5a
-#define GPCMD_PAUSE_RESUME 0x4b
-#define GPCMD_PLAY_AUDIO_10 0x45
-#define GPCMD_PLAY_AUDIO_MSF 0x47
-#define GPCMD_PLAY_AUDIO_TI 0x48
-#define GPCMD_PLAY_CD 0xbc
-#define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1e
-#define GPCMD_READ_10 0x28
-#define GPCMD_READ_12 0xa8
-#define GPCMD_READ_CDVD_CAPACITY 0x25
-#define GPCMD_READ_CD 0xbe
-#define GPCMD_READ_CD_MSF 0xb9
-#define GPCMD_READ_DISC_INFO 0x51
-#define GPCMD_READ_DVD_STRUCTURE 0xad
-#define GPCMD_READ_FORMAT_CAPACITIES 0x23
-#define GPCMD_READ_HEADER 0x44
-#define GPCMD_READ_TRACK_RZONE_INFO 0x52
-#define GPCMD_READ_SUBCHANNEL 0x42
-#define GPCMD_READ_TOC_PMA_ATIP 0x43
-#define GPCMD_REPAIR_RZONE_TRACK 0x58
-#define GPCMD_REPORT_KEY 0xa4
-#define GPCMD_REQUEST_SENSE 0x03
-#define GPCMD_RESERVE_RZONE_TRACK 0x53
-#define GPCMD_SCAN 0xba
-#define GPCMD_SEEK 0x2b
-#define GPCMD_SEND_DVD_STRUCTURE 0xad
-#define GPCMD_SEND_EVENT 0xa2
-#define GPCMD_SEND_KEY 0xa3
-#define GPCMD_SEND_OPC 0x54
-#define GPCMD_SET_READ_AHEAD 0xa7
-#define GPCMD_SET_STREAMING 0xb6
-#define GPCMD_START_STOP_UNIT 0x1b
-#define GPCMD_STOP_PLAY_SCAN 0x4e
-#define GPCMD_TEST_UNIT_READY 0x00
-#define GPCMD_VERIFY_10 0x2f
-#define GPCMD_WRITE_10 0x2a
-#define GPCMD_WRITE_AND_VERIFY_10 0x2e
-/* This is listed as optional in ATAPI 2.6, but is (curiously)
- * missing from Mt. Fuji, Table 57. It _is_ mentioned in Mt. Fuji
- * Table 377 as an MMC command for SCSi devices though... Most ATAPI
- * drives support it. */
-#define GPCMD_SET_SPEED 0xbb
-/* This seems to be a SCSI specific CD-ROM opcode
- * to play data at track/index */
-#define GPCMD_PLAYAUDIO_TI 0x48
-/*
- * From MS Media Status Notification Support Specification. For
- * older drives only.
- */
-#define GPCMD_GET_MEDIA_STATUS 0xda
-#define GPCMD_MODE_SENSE_6 0x1a
-
-/* Mode page codes for mode sense/set */
-#define GPMODE_R_W_ERROR_PAGE 0x01
-#define GPMODE_WRITE_PARMS_PAGE 0x05
-#define GPMODE_AUDIO_CTL_PAGE 0x0e
-#define GPMODE_POWER_PAGE 0x1a
-#define GPMODE_FAULT_FAIL_PAGE 0x1c
-#define GPMODE_TO_PROTECT_PAGE 0x1d
-#define GPMODE_CAPABILITIES_PAGE 0x2a
-#define GPMODE_ALL_PAGES 0x3f
-/* Not in Mt. Fuji, but in ATAPI 2.6 -- depricated now in favor
- * of MODE_SENSE_POWER_PAGE */
-#define GPMODE_CDROM_PAGE 0x0d
-
-/*
- * Based on values from <linux/cdrom.h> but extending CD_MINS
- * to the maximum common size allowed by the Orange's Book ATIP
- *
- * 90 and 99 min CDs are also available but using them as the
- * upper limit reduces the effectiveness of the heuristic to
- * detect DVDs burned to less than 25% of their maximum capacity
- */
-
-/* Some generally useful CD-ROM information */
-#define CD_MINS 80 /* max. minutes per CD */
-#define CD_SECS 60 /* seconds per minute */
-#define CD_FRAMES 75 /* frames per second */
-#define CD_FRAMESIZE 2048 /* bytes per frame, "cooked" mode */
-#define CD_MAX_BYTES (CD_MINS * CD_SECS * CD_FRAMES * CD_FRAMESIZE)
-#define CD_MAX_SECTORS (CD_MAX_BYTES / 512)
-
-/*
- * The MMC values are not IDE specific and might need to be moved
- * to a common header if they are also needed for the SCSI emulation
- */
-
-/* Profile list from MMC-6 revision 1 table 91 */
-#define MMC_PROFILE_NONE 0x0000
-#define MMC_PROFILE_CD_ROM 0x0008
-#define MMC_PROFILE_CD_R 0x0009
-#define MMC_PROFILE_CD_RW 0x000A
-#define MMC_PROFILE_DVD_ROM 0x0010
-#define MMC_PROFILE_DVD_R_SR 0x0011
-#define MMC_PROFILE_DVD_RAM 0x0012
-#define MMC_PROFILE_DVD_RW_RO 0x0013
-#define MMC_PROFILE_DVD_RW_SR 0x0014
-#define MMC_PROFILE_DVD_R_DL_SR 0x0015
-#define MMC_PROFILE_DVD_R_DL_JR 0x0016
-#define MMC_PROFILE_DVD_RW_DL 0x0017
-#define MMC_PROFILE_DVD_DDR 0x0018
-#define MMC_PROFILE_DVD_PLUS_RW 0x001A
-#define MMC_PROFILE_DVD_PLUS_R 0x001B
-#define MMC_PROFILE_DVD_PLUS_RW_DL 0x002A
-#define MMC_PROFILE_DVD_PLUS_R_DL 0x002B
-#define MMC_PROFILE_BD_ROM 0x0040
-#define MMC_PROFILE_BD_R_SRM 0x0041
-#define MMC_PROFILE_BD_R_RRM 0x0042
-#define MMC_PROFILE_BD_RE 0x0043
-#define MMC_PROFILE_HDDVD_ROM 0x0050
-#define MMC_PROFILE_HDDVD_R 0x0051
-#define MMC_PROFILE_HDDVD_RAM 0x0052
-#define MMC_PROFILE_HDDVD_RW 0x0053
-#define MMC_PROFILE_HDDVD_R_DL 0x0058
-#define MMC_PROFILE_HDDVD_RW_DL 0x005A
-#define MMC_PROFILE_INVALID 0xFFFF
-
-#define ATAPI_INT_REASON_CD 0x01 /* 0 = data transfer */
-#define ATAPI_INT_REASON_IO 0x02 /* 1 = transfer to the host */
-#define ATAPI_INT_REASON_REL 0x04
-#define ATAPI_INT_REASON_TAG 0xf8
-
-/* same constants as bochs */
-#define ASC_ILLEGAL_OPCODE 0x20
-#define ASC_LOGICAL_BLOCK_OOR 0x21
-#define ASC_INV_FIELD_IN_CMD_PACKET 0x24
-#define ASC_MEDIUM_MAY_HAVE_CHANGED 0x28
-#define ASC_INCOMPATIBLE_FORMAT 0x30
-#define ASC_MEDIUM_NOT_PRESENT 0x3a
-#define ASC_SAVING_PARAMETERS_NOT_SUPPORTED 0x39
-#define ASC_MEDIA_REMOVAL_PREVENTED 0x53
-
-#define CFA_NO_ERROR 0x00
-#define CFA_MISC_ERROR 0x09
-#define CFA_INVALID_COMMAND 0x20
-#define CFA_INVALID_ADDRESS 0x21
-#define CFA_ADDRESS_OVERFLOW 0x2f
-
-#define SENSE_NONE 0
-#define SENSE_NOT_READY 2
-#define SENSE_ILLEGAL_REQUEST 5
-#define SENSE_UNIT_ATTENTION 6
-
/* XXX: DVDs that could fit on a CD will be reported as a CD */
static inline int media_present(IDEState *s)
{
@@ -636,17 +298,6 @@ static inline void ide_dma_submit_check(IDEState *s,
dma_cb(bm, -1);
}
-static inline void ide_set_irq(IDEState *s)
-{
- BMDMAState *bm = s->bus->bmdma;
- if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
- if (bm) {
- bm->status |= BM_STATUS_INT;
- }
- qemu_irq_raise(s->irq);
- }
-}
-
/* prepare data transfer and tell what to do after */
static void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
EndTransferFunc *end_transfer_func)
@@ -666,7 +317,7 @@ static void ide_transfer_stop(IDEState *s)
s->status &= ~DRQ_STAT;
}
-static int64_t ide_get_sector(IDEState *s)
+int64_t ide_get_sector(IDEState *s)
{
int64_t sector_num;
if (s->select & 0x40) {
@@ -688,7 +339,7 @@ static int64_t ide_get_sector(IDEState *s)
return sector_num;
}
-static void ide_set_sector(IDEState *s, int64_t sector_num)
+void ide_set_sector(IDEState *s, int64_t sector_num)
{
unsigned int cyl, r;
if (s->select & 0x40) {
@@ -796,7 +447,7 @@ static void dma_buf_commit(IDEState *s, int is_write)
qemu_sglist_destroy(&s->sg);
}
-static void ide_dma_error(IDEState *s)
+void ide_dma_error(IDEState *s)
{
ide_transfer_stop(s);
s->error = ABRT_ERR;
@@ -1072,7 +723,7 @@ static void ide_sector_write_dma(IDEState *s)
ide_dma_start(s, ide_write_dma_cb);
}
-static void ide_atapi_cmd_ok(IDEState *s)
+void ide_atapi_cmd_ok(IDEState *s)
{
s->error = 0;
s->status = READY_STAT | SEEK_STAT;
@@ -1080,7 +731,7 @@ static void ide_atapi_cmd_ok(IDEState *s)
ide_set_irq(s);
}
-static void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
+void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
{
#ifdef DEBUG_IDE_ATAPI
printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key, asc);
@@ -1175,7 +826,7 @@ static int cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf,
return ret;
}
-static void ide_atapi_io_error(IDEState *s, int ret)
+void ide_atapi_io_error(IDEState *s, int ret)
{
/* XXX: handle more errors */
if (ret == -ENOMEDIUM) {
@@ -2667,7 +2318,7 @@ static void ide_dummy_transfer_stop(IDEState *s)
s->io_buffer[3] = 0xff;
}
-static void ide_reset(IDEState *s)
+void ide_reset(IDEState *s)
{
IDEBus *bus = s->bus;
@@ -2873,331 +2524,6 @@ void ide_dma_cancel(BMDMAState *bm)
}
}
-#if defined(TARGET_PPC)
-/***********************************************************/
-/* MacIO based PowerPC IDE */
-
-typedef struct MACIOIDEState {
- IDEBus bus;
- BlockDriverAIOCB *aiocb;
-} MACIOIDEState;
-
-static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
-{
- DBDMA_io *io = opaque;
- MACIOIDEState *m = io->opaque;
- IDEState *s = idebus_active_if(&m->bus);
-
- if (ret < 0) {
- m->aiocb = NULL;
- qemu_sglist_destroy(&s->sg);
- ide_atapi_io_error(s, ret);
- io->dma_end(opaque);
- return;
- }
-
- if (s->io_buffer_size > 0) {
- m->aiocb = NULL;
- qemu_sglist_destroy(&s->sg);
-
- s->packet_transfer_size -= s->io_buffer_size;
-
- s->io_buffer_index += s->io_buffer_size;
- s->lba += s->io_buffer_index >> 11;
- s->io_buffer_index &= 0x7ff;
- }
-
- if (s->packet_transfer_size <= 0)
- ide_atapi_cmd_ok(s);
-
- if (io->len == 0) {
- io->dma_end(opaque);
- return;
- }
-
- /* launch next transfer */
-
- s->io_buffer_size = io->len;
-
- qemu_sglist_init(&s->sg, io->len / TARGET_PAGE_SIZE + 1);
- qemu_sglist_add(&s->sg, io->addr, io->len);
- io->addr += io->len;
- io->len = 0;
-
- m->aiocb = dma_bdrv_read(s->bs, &s->sg,
- (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
- pmac_ide_atapi_transfer_cb, io);
- if (!m->aiocb) {
- qemu_sglist_destroy(&s->sg);
- /* Note: media not present is the most likely case */
- ide_atapi_cmd_error(s, SENSE_NOT_READY,
- ASC_MEDIUM_NOT_PRESENT);
- io->dma_end(opaque);
- return;
- }
-}
-
-static void pmac_ide_transfer_cb(void *opaque, int ret)
-{
- DBDMA_io *io = opaque;
- MACIOIDEState *m = io->opaque;
- IDEState *s = idebus_active_if(&m->bus);
- int n;
- int64_t sector_num;
-
- if (ret < 0) {
- m->aiocb = NULL;
- qemu_sglist_destroy(&s->sg);
- ide_dma_error(s);
- io->dma_end(io);
- return;
- }
-
- sector_num = ide_get_sector(s);
- if (s->io_buffer_size > 0) {
- m->aiocb = NULL;
- qemu_sglist_destroy(&s->sg);
- n = (s->io_buffer_size + 0x1ff) >> 9;
- sector_num += n;
- ide_set_sector(s, sector_num);
- s->nsector -= n;
- }
-
- /* end of transfer ? */
- if (s->nsector == 0) {
- s->status = READY_STAT | SEEK_STAT;
- ide_set_irq(s);
- }
-
- /* end of DMA ? */
-
- if (io->len == 0) {
- io->dma_end(io);
- return;
- }
-
- /* launch next transfer */
-
- s->io_buffer_index = 0;
- s->io_buffer_size = io->len;
-
- qemu_sglist_init(&s->sg, io->len / TARGET_PAGE_SIZE + 1);
- qemu_sglist_add(&s->sg, io->addr, io->len);
- io->addr += io->len;
- io->len = 0;
-
- if (s->is_read)
- m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
- pmac_ide_transfer_cb, io);
- else
- m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
- pmac_ide_transfer_cb, io);
- if (!m->aiocb)
- pmac_ide_transfer_cb(io, -1);
-}
-
-static void pmac_ide_transfer(DBDMA_io *io)
-{
- MACIOIDEState *m = io->opaque;
- IDEState *s = idebus_active_if(&m->bus);
-
- s->io_buffer_size = 0;
- if (s->is_cdrom) {
- pmac_ide_atapi_transfer_cb(io, 0);
- return;
- }
-
- pmac_ide_transfer_cb(io, 0);
-}
-
-static void pmac_ide_flush(DBDMA_io *io)
-{
- MACIOIDEState *m = io->opaque;
-
- if (m->aiocb)
- qemu_aio_flush();
-}
-
-/* PowerMac IDE memory IO */
-static void pmac_ide_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t val)
-{
- MACIOIDEState *d = opaque;
-
- addr = (addr & 0xFFF) >> 4;
- switch (addr) {
- case 1 ... 7:
- ide_ioport_write(&d->bus, addr, val);
- break;
- case 8:
- case 22:
- ide_cmd_write(&d->bus, 0, val);
- break;
- default:
- break;
- }
-}
-
-static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
-{
- uint8_t retval;
- MACIOIDEState *d = opaque;
-
- addr = (addr & 0xFFF) >> 4;
- switch (addr) {
- case 1 ... 7:
- retval = ide_ioport_read(&d->bus, addr);
- break;
- case 8:
- case 22:
- retval = ide_status_read(&d->bus, 0);
- break;
- default:
- retval = 0xFF;
- break;
- }
- return retval;
-}
-
-static void pmac_ide_writew (void *opaque,
- target_phys_addr_t addr, uint32_t val)
-{
- MACIOIDEState *d = opaque;
-
- addr = (addr & 0xFFF) >> 4;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap16(val);
-#endif
- if (addr == 0) {
- ide_data_writew(&d->bus, 0, val);
- }
-}
-
-static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
-{
- uint16_t retval;
- MACIOIDEState *d = opaque;
-
- addr = (addr & 0xFFF) >> 4;
- if (addr == 0) {
- retval = ide_data_readw(&d->bus, 0);
- } else {
- retval = 0xFFFF;
- }
-#ifdef TARGET_WORDS_BIGENDIAN
- retval = bswap16(retval);
-#endif
- return retval;
-}
-
-static void pmac_ide_writel (void *opaque,
- target_phys_addr_t addr, uint32_t val)
-{
- MACIOIDEState *d = opaque;
-
- addr = (addr & 0xFFF) >> 4;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
- if (addr == 0) {
- ide_data_writel(&d->bus, 0, val);
- }
-}
-
-static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
-{
- uint32_t retval;
- MACIOIDEState *d = opaque;
-
- addr = (addr & 0xFFF) >> 4;
- if (addr == 0) {
- retval = ide_data_readl(&d->bus, 0);
- } else {
- retval = 0xFFFFFFFF;
- }
-#ifdef TARGET_WORDS_BIGENDIAN
- retval = bswap32(retval);
-#endif
- return retval;
-}
-
-static CPUWriteMemoryFunc *pmac_ide_write[] = {
- pmac_ide_writeb,
- pmac_ide_writew,
- pmac_ide_writel,
-};
-
-static CPUReadMemoryFunc *pmac_ide_read[] = {
- pmac_ide_readb,
- pmac_ide_readw,
- pmac_ide_readl,
-};
-
-static void pmac_ide_save(QEMUFile *f, void *opaque)
-{
- MACIOIDEState *d = opaque;
- unsigned int i;
-
- /* per IDE interface data */
- idebus_save(f, &d->bus);
-
- /* per IDE drive data */
- for(i = 0; i < 2; i++) {
- ide_save(f, &d->bus.ifs[i]);
- }
-}
-
-static int pmac_ide_load(QEMUFile *f, void *opaque, int version_id)
-{
- MACIOIDEState *d = opaque;
- unsigned int i;
-
- if (version_id != 1 && version_id != 3)
- return -EINVAL;
-
- /* per IDE interface data */
- idebus_load(f, &d->bus, version_id);
-
- /* per IDE drive data */
- for(i = 0; i < 2; i++) {
- ide_load(f, &d->bus.ifs[i], version_id);
- }
- return 0;
-}
-
-static void pmac_ide_reset(void *opaque)
-{
- MACIOIDEState *d = opaque;
-
- ide_reset(d->bus.ifs +0);
- ide_reset(d->bus.ifs +1);
-}
-
-/* hd_table must contain 4 block drivers */
-/* PowerMac uses memory mapped registers, not I/O. Return the memory
- I/O index to access the ide. */
-int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
- void *dbdma, int channel, qemu_irq dma_irq)
-{
- MACIOIDEState *d;
- int pmac_ide_memory;
-
- d = qemu_mallocz(sizeof(MACIOIDEState));
- ide_init2(&d->bus, hd_table[0], hd_table[1], irq);
-
- if (dbdma)
- DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
-
- pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
- pmac_ide_write, d);
- register_savevm("ide", 0, 3, pmac_ide_save, pmac_ide_load, d);
- qemu_register_reset(pmac_ide_reset, d);
- pmac_ide_reset(d);
-
- return pmac_ide_memory;
-}
-#endif /* TARGET_PPC */
-
/***********************************************************/
/* MMIO based ide port
* This emulates IDE device connected directly to the CPU bus without
diff --git a/hw/ide.h b/hw/ide.h
index faa04a3..02aa686 100644
--- a/hw/ide.h
+++ b/hw/ide.h
@@ -15,4 +15,8 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
qemu_irq *pic);
+/* ide-macio.c */
+int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
+ void *dbdma, int channel, qemu_irq dma_irq);
+
#endif /* HW_IDE_H */
diff --git a/hw/ppc_mac.h b/hw/ppc_mac.h
index bcc4aaf..a04dffe 100644
--- a/hw/ppc_mac.h
+++ b/hw/ppc_mac.h
@@ -49,10 +49,6 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
int dbdma_mem_index, int cuda_mem_index, void *nvram,
int nb_ide, int *ide_mem_index, int escc_mem_index);
-/* NewWorld PowerMac IDE */
-int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
- void *dbdma, int channel, qemu_irq dma_irq);
-
/* Heathrow PIC */
qemu_irq *heathrow_pic_init(int *pmem_index,
int nb_cpus, qemu_irq **irqs);
--
1.6.2.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Qemu-devel] [PATCH 6/8] ide: split away ide-mmio.c
2009-08-18 16:06 [Qemu-devel] [PATCH 0/8] ide: cleanup and splitting Gerd Hoffmann
` (4 preceding siblings ...)
2009-08-18 16:06 ` [Qemu-devel] [PATCH 5/8] ide: split away ide-macio.c Gerd Hoffmann
@ 2009-08-18 16:06 ` Gerd Hoffmann
2009-08-18 16:06 ` [Qemu-devel] [PATCH 7/8] ide: add save/restore support for mmio Gerd Hoffmann
` (2 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Gerd Hoffmann @ 2009-08-18 16:06 UTC (permalink / raw)
To: qemu-devel; +Cc: Gerd Hoffmann
create ide-mmio.c and place mmio support there.
only build ide-mmio support for platforms using it.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
Makefile.target | 2 +-
hw/ide-mmio.c | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/ide.c | 92 -----------------------------------------
hw/ide.h | 5 ++
hw/r2d.c | 1 +
hw/sh.h | 4 --
6 files changed, 130 insertions(+), 97 deletions(-)
create mode 100644 hw/ide-mmio.c
diff --git a/Makefile.target b/Makefile.target
index 08afa82..9fd4cbf 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -277,7 +277,7 @@ obj-arm-y += syborg_virtio.o
obj-sh4-y = shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
obj-sh4-y += sh_timer.o sh_serial.o sh_intc.o sh_pci.o sm501.o serial.o
-obj-sh4-y += ide.o
+obj-sh4-y += ide.o ide-mmio.o
obj-m68k-y = an5206.o mcf5206.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
obj-m68k-y += m68k-semi.o dummy_m68k.o
diff --git a/hw/ide-mmio.c b/hw/ide-mmio.c
new file mode 100644
index 0000000..4608dcf
--- /dev/null
+++ b/hw/ide-mmio.c
@@ -0,0 +1,123 @@
+/*
+ * QEMU IDE disk and CD/DVD-ROM Emulator
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2006 Openedhand Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "block.h"
+#include "block_int.h"
+#include "sysemu.h"
+#include "dma.h"
+#include "ide-internal.h"
+
+/***********************************************************/
+/* MMIO based ide port
+ * This emulates IDE device connected directly to the CPU bus without
+ * dedicated ide controller, which is often seen on embedded boards.
+ */
+
+typedef struct {
+ IDEBus *bus;
+ int shift;
+} MMIOState;
+
+static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
+{
+ MMIOState *s = (MMIOState*)opaque;
+ IDEBus *bus = s->bus;
+ addr >>= s->shift;
+ if (addr & 7)
+ return ide_ioport_read(bus, addr);
+ else
+ return ide_data_readw(bus, 0);
+}
+
+static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
+ uint32_t val)
+{
+ MMIOState *s = (MMIOState*)opaque;
+ IDEBus *bus = s->bus;
+ addr >>= s->shift;
+ if (addr & 7)
+ ide_ioport_write(bus, addr, val);
+ else
+ ide_data_writew(bus, 0, val);
+}
+
+static CPUReadMemoryFunc *mmio_ide_reads[] = {
+ mmio_ide_read,
+ mmio_ide_read,
+ mmio_ide_read,
+};
+
+static CPUWriteMemoryFunc *mmio_ide_writes[] = {
+ mmio_ide_write,
+ mmio_ide_write,
+ mmio_ide_write,
+};
+
+static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
+{
+ MMIOState *s= (MMIOState*)opaque;
+ IDEBus *bus = s->bus;
+ return ide_status_read(bus, 0);
+}
+
+static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
+ uint32_t val)
+{
+ MMIOState *s = (MMIOState*)opaque;
+ IDEBus *bus = s->bus;
+ ide_cmd_write(bus, 0, val);
+}
+
+static CPUReadMemoryFunc *mmio_ide_status[] = {
+ mmio_ide_status_read,
+ mmio_ide_status_read,
+ mmio_ide_status_read,
+};
+
+static CPUWriteMemoryFunc *mmio_ide_cmd[] = {
+ mmio_ide_cmd_write,
+ mmio_ide_cmd_write,
+ mmio_ide_cmd_write,
+};
+
+void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
+ qemu_irq irq, int shift,
+ BlockDriverState *hd0, BlockDriverState *hd1)
+{
+ MMIOState *s = qemu_mallocz(sizeof(MMIOState));
+ IDEBus *bus = qemu_mallocz(sizeof(*bus));
+ int mem1, mem2;
+
+ ide_init2(bus, hd0, hd1, irq);
+
+ s->bus = bus;
+ s->shift = shift;
+
+ mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s);
+ mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s);
+ cpu_register_physical_memory(membase, 16 << shift, mem1);
+ cpu_register_physical_memory(membase2, 2 << shift, mem2);
+}
+
diff --git a/hw/ide.c b/hw/ide.c
index d6c7dbd..01566ac 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -2525,98 +2525,6 @@ void ide_dma_cancel(BMDMAState *bm)
}
/***********************************************************/
-/* MMIO based ide port
- * This emulates IDE device connected directly to the CPU bus without
- * dedicated ide controller, which is often seen on embedded boards.
- */
-
-typedef struct {
- IDEBus *bus;
- int shift;
-} MMIOState;
-
-static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
-{
- MMIOState *s = (MMIOState*)opaque;
- IDEBus *bus = s->bus;
- addr >>= s->shift;
- if (addr & 7)
- return ide_ioport_read(bus, addr);
- else
- return ide_data_readw(bus, 0);
-}
-
-static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- MMIOState *s = (MMIOState*)opaque;
- IDEBus *bus = s->bus;
- addr >>= s->shift;
- if (addr & 7)
- ide_ioport_write(bus, addr, val);
- else
- ide_data_writew(bus, 0, val);
-}
-
-static CPUReadMemoryFunc *mmio_ide_reads[] = {
- mmio_ide_read,
- mmio_ide_read,
- mmio_ide_read,
-};
-
-static CPUWriteMemoryFunc *mmio_ide_writes[] = {
- mmio_ide_write,
- mmio_ide_write,
- mmio_ide_write,
-};
-
-static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
-{
- MMIOState *s= (MMIOState*)opaque;
- IDEBus *bus = s->bus;
- return ide_status_read(bus, 0);
-}
-
-static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- MMIOState *s = (MMIOState*)opaque;
- IDEBus *bus = s->bus;
- ide_cmd_write(bus, 0, val);
-}
-
-static CPUReadMemoryFunc *mmio_ide_status[] = {
- mmio_ide_status_read,
- mmio_ide_status_read,
- mmio_ide_status_read,
-};
-
-static CPUWriteMemoryFunc *mmio_ide_cmd[] = {
- mmio_ide_cmd_write,
- mmio_ide_cmd_write,
- mmio_ide_cmd_write,
-};
-
-void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
- qemu_irq irq, int shift,
- BlockDriverState *hd0, BlockDriverState *hd1)
-{
- MMIOState *s = qemu_mallocz(sizeof(MMIOState));
- IDEBus *bus = qemu_mallocz(sizeof(*bus));
- int mem1, mem2;
-
- ide_init2(bus, hd0, hd1, irq);
-
- s->bus = bus;
- s->shift = shift;
-
- mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s);
- mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s);
- cpu_register_physical_memory(membase, 16 << shift, mem1);
- cpu_register_physical_memory(membase2, 2 << shift, mem2);
-}
-
-/***********************************************************/
/* CF-ATA Microdrive */
#define METADATA_SIZE 0x20
diff --git a/hw/ide.h b/hw/ide.h
index 02aa686..56cf4ec 100644
--- a/hw/ide.h
+++ b/hw/ide.h
@@ -19,4 +19,9 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
void *dbdma, int channel, qemu_irq dma_irq);
+/* ide-mmio.c */
+void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
+ qemu_irq irq, int shift,
+ BlockDriverState *hd0, BlockDriverState *hd1);
+
#endif /* HW_IDE_H */
diff --git a/hw/r2d.c b/hw/r2d.c
index 697bcb6..64d5e4d 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -31,6 +31,7 @@
#include "pci.h"
#include "net.h"
#include "sh7750_regs.h"
+#include "ide.h"
#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
#define SDRAM_SIZE 0x04000000
diff --git a/hw/sh.h b/hw/sh.h
index 5e3c22b..d30e9f5 100644
--- a/hw/sh.h
+++ b/hw/sh.h
@@ -51,8 +51,4 @@ qemu_irq sh7750_irl(struct SH7750State *s);
/* tc58128.c */
int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2);
-/* ide.c */
-void mmio_ide_init(target_phys_addr_t membase, target_phys_addr_t membase2,
- qemu_irq irq, int shift,
- BlockDriverState *hd0, BlockDriverState *hd1);
#endif
--
1.6.2.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Qemu-devel] [PATCH 7/8] ide: add save/restore support for mmio
2009-08-18 16:06 [Qemu-devel] [PATCH 0/8] ide: cleanup and splitting Gerd Hoffmann
` (5 preceding siblings ...)
2009-08-18 16:06 ` [Qemu-devel] [PATCH 6/8] ide: split away ide-mmio.c Gerd Hoffmann
@ 2009-08-18 16:06 ` Gerd Hoffmann
2009-08-19 10:07 ` [Qemu-devel] " Juan Quintela
2009-08-18 16:06 ` [Qemu-devel] [PATCH 8/8] ide: split away ide-microdrive.c Gerd Hoffmann
2009-08-18 17:08 ` [Qemu-devel] [PATCH 0/8] ide: cleanup and splitting Avi Kivity
8 siblings, 1 reply; 15+ messages in thread
From: Gerd Hoffmann @ 2009-08-18 16:06 UTC (permalink / raw)
To: qemu-devel; +Cc: Gerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
hw/ide-mmio.c | 20 ++++++++++++++++++++
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/hw/ide-mmio.c b/hw/ide-mmio.c
index 4608dcf..28ef7fb 100644
--- a/hw/ide-mmio.c
+++ b/hw/ide-mmio.c
@@ -102,6 +102,25 @@ static CPUWriteMemoryFunc *mmio_ide_cmd[] = {
mmio_ide_cmd_write,
};
+static void mmio_ide_save(QEMUFile* f, void *opaque)
+{
+ MMIOState *s = opaque;
+
+ idebus_save(f, s->bus);
+ ide_save(f, &s->bus->ifs[0]);
+ ide_save(f, &s->bus->ifs[1]);
+}
+
+static int mmio_ide_load(QEMUFile* f, void *opaque, int version_id)
+{
+ MMIOState *s = opaque;
+
+ idebus_load(f, s->bus, version_id);
+ ide_load(f, &s->bus->ifs[0], version_id);
+ ide_load(f, &s->bus->ifs[1], version_id);
+ return 0;
+}
+
void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
qemu_irq irq, int shift,
BlockDriverState *hd0, BlockDriverState *hd1)
@@ -119,5 +138,6 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s);
cpu_register_physical_memory(membase, 16 << shift, mem1);
cpu_register_physical_memory(membase2, 2 << shift, mem2);
+ register_savevm("mmio-ide", 0, 3, mmio_ide_save, mmio_ide_load, s);
}
--
1.6.2.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* [Qemu-devel] [PATCH 8/8] ide: split away ide-microdrive.c
2009-08-18 16:06 [Qemu-devel] [PATCH 0/8] ide: cleanup and splitting Gerd Hoffmann
` (6 preceding siblings ...)
2009-08-18 16:06 ` [Qemu-devel] [PATCH 7/8] ide: add save/restore support for mmio Gerd Hoffmann
@ 2009-08-18 16:06 ` Gerd Hoffmann
2009-08-18 17:08 ` [Qemu-devel] [PATCH 0/8] ide: cleanup and splitting Avi Kivity
8 siblings, 0 replies; 15+ messages in thread
From: Gerd Hoffmann @ 2009-08-18 16:06 UTC (permalink / raw)
To: qemu-devel; +Cc: Gerd Hoffmann
create ide-microdrive.c and place microdrive support there.
only build ide-microdrive support for platforms using it.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
Makefile.target | 2 +-
hw/ide-microdrive.c | 574 +++++++++++++++++++++++++++++++++++++++++++++++++++
hw/ide.c | 542 ------------------------------------------------
3 files changed, 575 insertions(+), 543 deletions(-)
create mode 100644 hw/ide-microdrive.c
diff --git a/Makefile.target b/Makefile.target
index 9fd4cbf..148c5b0 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -263,7 +263,7 @@ obj-arm-y += arm-semi.o
obj-arm-y += pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
obj-arm-y += pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
obj-arm-y += pflash_cfi01.o gumstix.o
-obj-arm-y += zaurus.o ide.o serial.o spitz.o tosa.o tc6393xb.o
+obj-arm-y += zaurus.o ide.o ide-microdrive.o serial.o spitz.o tosa.o tc6393xb.o
obj-arm-y += omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o
obj-arm-y += omap2.o omap_dss.o soc_dma.o
obj-arm-y += omap_sx1.o palm.o tsc210x.o
diff --git a/hw/ide-microdrive.c b/hw/ide-microdrive.c
new file mode 100644
index 0000000..4baceea
--- /dev/null
+++ b/hw/ide-microdrive.c
@@ -0,0 +1,574 @@
+/*
+ * QEMU IDE disk and CD/DVD-ROM Emulator
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2006 Openedhand Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "pc.h"
+#include "block.h"
+#include "block_int.h"
+#include "sysemu.h"
+#include "dma.h"
+#include "ide-internal.h"
+#include "pcmcia.h"
+
+/***********************************************************/
+/* CF-ATA Microdrive */
+
+#define METADATA_SIZE 0x20
+
+/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
+typedef struct {
+ IDEBus bus;
+ PCMCIACardState card;
+ uint32_t attr_base;
+ uint32_t io_base;
+
+ /* Card state */
+ uint8_t opt;
+ uint8_t stat;
+ uint8_t pins;
+
+ uint8_t ctrl;
+ uint16_t io;
+ int cycle;
+} MicroDriveState;
+
+/* Register bitfields */
+enum md_opt {
+ OPT_MODE_MMAP = 0,
+ OPT_MODE_IOMAP16 = 1,
+ OPT_MODE_IOMAP1 = 2,
+ OPT_MODE_IOMAP2 = 3,
+ OPT_MODE = 0x3f,
+ OPT_LEVIREQ = 0x40,
+ OPT_SRESET = 0x80,
+};
+enum md_cstat {
+ STAT_INT = 0x02,
+ STAT_PWRDWN = 0x04,
+ STAT_XE = 0x10,
+ STAT_IOIS8 = 0x20,
+ STAT_SIGCHG = 0x40,
+ STAT_CHANGED = 0x80,
+};
+enum md_pins {
+ PINS_MRDY = 0x02,
+ PINS_CRDY = 0x20,
+};
+enum md_ctrl {
+ CTRL_IEN = 0x02,
+ CTRL_SRST = 0x04,
+};
+
+static inline void md_interrupt_update(MicroDriveState *s)
+{
+ if (!s->card.slot)
+ return;
+
+ qemu_set_irq(s->card.slot->irq,
+ !(s->stat & STAT_INT) && /* Inverted */
+ !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
+ !(s->opt & OPT_SRESET));
+}
+
+static void md_set_irq(void *opaque, int irq, int level)
+{
+ MicroDriveState *s = (MicroDriveState *) opaque;
+ if (level)
+ s->stat |= STAT_INT;
+ else
+ s->stat &= ~STAT_INT;
+
+ md_interrupt_update(s);
+}
+
+static void md_reset(MicroDriveState *s)
+{
+ s->opt = OPT_MODE_MMAP;
+ s->stat = 0;
+ s->pins = 0;
+ s->cycle = 0;
+ s->ctrl = 0;
+ ide_reset(s->bus.ifs);
+}
+
+static uint8_t md_attr_read(void *opaque, uint32_t at)
+{
+ MicroDriveState *s = (MicroDriveState *) opaque;
+ if (at < s->attr_base) {
+ if (at < s->card.cis_len)
+ return s->card.cis[at];
+ else
+ return 0x00;
+ }
+
+ at -= s->attr_base;
+
+ switch (at) {
+ case 0x00: /* Configuration Option Register */
+ return s->opt;
+ case 0x02: /* Card Configuration Status Register */
+ if (s->ctrl & CTRL_IEN)
+ return s->stat & ~STAT_INT;
+ else
+ return s->stat;
+ case 0x04: /* Pin Replacement Register */
+ return (s->pins & PINS_CRDY) | 0x0c;
+ case 0x06: /* Socket and Copy Register */
+ return 0x00;
+#ifdef VERBOSE
+ default:
+ printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
+#endif
+ }
+
+ return 0;
+}
+
+static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
+{
+ MicroDriveState *s = (MicroDriveState *) opaque;
+ at -= s->attr_base;
+
+ switch (at) {
+ case 0x00: /* Configuration Option Register */
+ s->opt = value & 0xcf;
+ if (value & OPT_SRESET)
+ md_reset(s);
+ md_interrupt_update(s);
+ break;
+ case 0x02: /* Card Configuration Status Register */
+ if ((s->stat ^ value) & STAT_PWRDWN)
+ s->pins |= PINS_CRDY;
+ s->stat &= 0x82;
+ s->stat |= value & 0x74;
+ md_interrupt_update(s);
+ /* Word 170 in Identify Device must be equal to STAT_XE */
+ break;
+ case 0x04: /* Pin Replacement Register */
+ s->pins &= PINS_CRDY;
+ s->pins |= value & PINS_MRDY;
+ break;
+ case 0x06: /* Socket and Copy Register */
+ break;
+ default:
+ printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
+ }
+}
+
+static uint16_t md_common_read(void *opaque, uint32_t at)
+{
+ MicroDriveState *s = (MicroDriveState *) opaque;
+ IDEState *ifs;
+ uint16_t ret;
+ at -= s->io_base;
+
+ switch (s->opt & OPT_MODE) {
+ case OPT_MODE_MMAP:
+ if ((at & ~0x3ff) == 0x400)
+ at = 0;
+ break;
+ case OPT_MODE_IOMAP16:
+ at &= 0xf;
+ break;
+ case OPT_MODE_IOMAP1:
+ if ((at & ~0xf) == 0x3f0)
+ at -= 0x3e8;
+ else if ((at & ~0xf) == 0x1f0)
+ at -= 0x1f0;
+ break;
+ case OPT_MODE_IOMAP2:
+ if ((at & ~0xf) == 0x370)
+ at -= 0x368;
+ else if ((at & ~0xf) == 0x170)
+ at -= 0x170;
+ }
+
+ switch (at) {
+ case 0x0: /* Even RD Data */
+ case 0x8:
+ return ide_data_readw(&s->bus, 0);
+
+ /* TODO: 8-bit accesses */
+ if (s->cycle)
+ ret = s->io >> 8;
+ else {
+ s->io = ide_data_readw(&s->bus, 0);
+ ret = s->io & 0xff;
+ }
+ s->cycle = !s->cycle;
+ return ret;
+ case 0x9: /* Odd RD Data */
+ return s->io >> 8;
+ case 0xd: /* Error */
+ return ide_ioport_read(&s->bus, 0x1);
+ case 0xe: /* Alternate Status */
+ ifs = idebus_active_if(&s->bus);
+ if (ifs->bs)
+ return ifs->status;
+ else
+ return 0;
+ case 0xf: /* Device Address */
+ ifs = idebus_active_if(&s->bus);
+ return 0xc2 | ((~ifs->select << 2) & 0x3c);
+ default:
+ return ide_ioport_read(&s->bus, at);
+ }
+
+ return 0;
+}
+
+static void md_common_write(void *opaque, uint32_t at, uint16_t value)
+{
+ MicroDriveState *s = (MicroDriveState *) opaque;
+ at -= s->io_base;
+
+ switch (s->opt & OPT_MODE) {
+ case OPT_MODE_MMAP:
+ if ((at & ~0x3ff) == 0x400)
+ at = 0;
+ break;
+ case OPT_MODE_IOMAP16:
+ at &= 0xf;
+ break;
+ case OPT_MODE_IOMAP1:
+ if ((at & ~0xf) == 0x3f0)
+ at -= 0x3e8;
+ else if ((at & ~0xf) == 0x1f0)
+ at -= 0x1f0;
+ break;
+ case OPT_MODE_IOMAP2:
+ if ((at & ~0xf) == 0x370)
+ at -= 0x368;
+ else if ((at & ~0xf) == 0x170)
+ at -= 0x170;
+ }
+
+ switch (at) {
+ case 0x0: /* Even WR Data */
+ case 0x8:
+ ide_data_writew(&s->bus, 0, value);
+ break;
+
+ /* TODO: 8-bit accesses */
+ if (s->cycle)
+ ide_data_writew(&s->bus, 0, s->io | (value << 8));
+ else
+ s->io = value & 0xff;
+ s->cycle = !s->cycle;
+ break;
+ case 0x9:
+ s->io = value & 0xff;
+ s->cycle = !s->cycle;
+ break;
+ case 0xd: /* Features */
+ ide_ioport_write(&s->bus, 0x1, value);
+ break;
+ case 0xe: /* Device Control */
+ s->ctrl = value;
+ if (value & CTRL_SRST)
+ md_reset(s);
+ md_interrupt_update(s);
+ break;
+ default:
+ if (s->stat & STAT_PWRDWN) {
+ s->pins |= PINS_CRDY;
+ s->stat &= ~STAT_PWRDWN;
+ }
+ ide_ioport_write(&s->bus, at, value);
+ }
+}
+
+static void md_save(QEMUFile *f, void *opaque)
+{
+ MicroDriveState *s = (MicroDriveState *) opaque;
+ int i;
+
+ qemu_put_8s(f, &s->opt);
+ qemu_put_8s(f, &s->stat);
+ qemu_put_8s(f, &s->pins);
+
+ qemu_put_8s(f, &s->ctrl);
+ qemu_put_be16s(f, &s->io);
+ qemu_put_byte(f, s->cycle);
+
+ idebus_save(f, &s->bus);
+
+ for (i = 0; i < 2; i ++)
+ ide_save(f, &s->bus.ifs[i]);
+}
+
+static int md_load(QEMUFile *f, void *opaque, int version_id)
+{
+ MicroDriveState *s = (MicroDriveState *) opaque;
+ int i;
+
+ if (version_id != 0 && version_id != 3)
+ return -EINVAL;
+
+ qemu_get_8s(f, &s->opt);
+ qemu_get_8s(f, &s->stat);
+ qemu_get_8s(f, &s->pins);
+
+ qemu_get_8s(f, &s->ctrl);
+ qemu_get_be16s(f, &s->io);
+ s->cycle = qemu_get_byte(f);
+
+ idebus_load(f, &s->bus, version_id);
+
+ for (i = 0; i < 2; i ++)
+ ide_load(f, &s->bus.ifs[i], version_id);
+
+ return 0;
+}
+
+static const uint8_t dscm1xxxx_cis[0x14a] = {
+ [0x000] = CISTPL_DEVICE, /* 5V Device Information */
+ [0x002] = 0x03, /* Tuple length = 4 bytes */
+ [0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
+ [0x006] = 0x01, /* Size = 2K bytes */
+ [0x008] = CISTPL_ENDMARK,
+
+ [0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */
+ [0x00c] = 0x04, /* Tuple length = 4 byest */
+ [0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
+ [0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
+ [0x012] = 0x01, /* Size = 2K bytes */
+ [0x014] = CISTPL_ENDMARK,
+
+ [0x016] = CISTPL_JEDEC_C, /* JEDEC ID */
+ [0x018] = 0x02, /* Tuple length = 2 bytes */
+ [0x01a] = 0xdf, /* PC Card ATA with no Vpp required */
+ [0x01c] = 0x01,
+
+ [0x01e] = CISTPL_MANFID, /* Manufacture ID */
+ [0x020] = 0x04, /* Tuple length = 4 bytes */
+ [0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */
+ [0x024] = 0x00,
+ [0x026] = 0x00, /* PLMID_CARD = 0000 */
+ [0x028] = 0x00,
+
+ [0x02a] = CISTPL_VERS_1, /* Level 1 Version */
+ [0x02c] = 0x12, /* Tuple length = 23 bytes */
+ [0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
+ [0x030] = 0x01, /* Minor Version = 1 */
+ [0x032] = 'I',
+ [0x034] = 'B',
+ [0x036] = 'M',
+ [0x038] = 0x00,
+ [0x03a] = 'm',
+ [0x03c] = 'i',
+ [0x03e] = 'c',
+ [0x040] = 'r',
+ [0x042] = 'o',
+ [0x044] = 'd',
+ [0x046] = 'r',
+ [0x048] = 'i',
+ [0x04a] = 'v',
+ [0x04c] = 'e',
+ [0x04e] = 0x00,
+ [0x050] = CISTPL_ENDMARK,
+
+ [0x052] = CISTPL_FUNCID, /* Function ID */
+ [0x054] = 0x02, /* Tuple length = 2 bytes */
+ [0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */
+ [0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
+
+ [0x05a] = CISTPL_FUNCE, /* Function Extension */
+ [0x05c] = 0x02, /* Tuple length = 2 bytes */
+ [0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */
+ [0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */
+
+ [0x062] = CISTPL_FUNCE, /* Function Extension */
+ [0x064] = 0x03, /* Tuple length = 3 bytes */
+ [0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */
+ [0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */
+ [0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
+
+ [0x06c] = CISTPL_CONFIG, /* Configuration */
+ [0x06e] = 0x05, /* Tuple length = 5 bytes */
+ [0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
+ [0x072] = 0x07, /* TPCC_LAST = 7 */
+ [0x074] = 0x00, /* TPCC_RADR = 0200 */
+ [0x076] = 0x02,
+ [0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */
+
+ [0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
+ [0x07c] = 0x0b, /* Tuple length = 11 bytes */
+ [0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */
+ [0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */
+ [0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
+ [0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
+ [0x086] = 0x55, /* NomV: 5.0 V */
+ [0x088] = 0x4d, /* MinV: 4.5 V */
+ [0x08a] = 0x5d, /* MaxV: 5.5 V */
+ [0x08c] = 0x4e, /* Peakl: 450 mA */
+ [0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */
+ [0x090] = 0x00, /* Window descriptor: Window length = 0 */
+ [0x092] = 0x20, /* TPCE_MI: support power down mode, RW */
+
+ [0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
+ [0x096] = 0x06, /* Tuple length = 6 bytes */
+ [0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */
+ [0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
+ [0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
+ [0x09e] = 0xb5, /* NomV: 3.3 V */
+ [0x0a0] = 0x1e,
+ [0x0a2] = 0x3e, /* Peakl: 350 mA */
+
+ [0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
+ [0x0a6] = 0x0d, /* Tuple length = 13 bytes */
+ [0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */
+ [0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
+ [0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
+ [0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
+ [0x0b0] = 0x55, /* NomV: 5.0 V */
+ [0x0b2] = 0x4d, /* MinV: 4.5 V */
+ [0x0b4] = 0x5d, /* MaxV: 5.5 V */
+ [0x0b6] = 0x4e, /* Peakl: 450 mA */
+ [0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */
+ [0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */
+ [0x0bc] = 0xff, /* IRQ0..IRQ7 supported */
+ [0x0be] = 0xff, /* IRQ8..IRQ15 supported */
+ [0x0c0] = 0x20, /* TPCE_MI = support power down mode */
+
+ [0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
+ [0x0c4] = 0x06, /* Tuple length = 6 bytes */
+ [0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */
+ [0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
+ [0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
+ [0x0cc] = 0xb5, /* NomV: 3.3 V */
+ [0x0ce] = 0x1e,
+ [0x0d0] = 0x3e, /* Peakl: 350 mA */
+
+ [0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
+ [0x0d4] = 0x12, /* Tuple length = 18 bytes */
+ [0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */
+ [0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
+ [0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
+ [0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
+ [0x0de] = 0x55, /* NomV: 5.0 V */
+ [0x0e0] = 0x4d, /* MinV: 4.5 V */
+ [0x0e2] = 0x5d, /* MaxV: 5.5 V */
+ [0x0e4] = 0x4e, /* Peakl: 450 mA */
+ [0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
+ [0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */
+ [0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */
+ [0x0ec] = 0x01,
+ [0x0ee] = 0x07, /* Address block length = 8 */
+ [0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */
+ [0x0f2] = 0x03,
+ [0x0f4] = 0x01, /* Address block length = 2 */
+ [0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
+ [0x0f8] = 0x20, /* TPCE_MI = support power down mode */
+
+ [0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
+ [0x0fc] = 0x06, /* Tuple length = 6 bytes */
+ [0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */
+ [0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
+ [0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
+ [0x104] = 0xb5, /* NomV: 3.3 V */
+ [0x106] = 0x1e,
+ [0x108] = 0x3e, /* Peakl: 350 mA */
+
+ [0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
+ [0x10c] = 0x12, /* Tuple length = 18 bytes */
+ [0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */
+ [0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
+ [0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
+ [0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
+ [0x116] = 0x55, /* NomV: 5.0 V */
+ [0x118] = 0x4d, /* MinV: 4.5 V */
+ [0x11a] = 0x5d, /* MaxV: 5.5 V */
+ [0x11c] = 0x4e, /* Peakl: 450 mA */
+ [0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
+ [0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */
+ [0x122] = 0x70, /* Field 1 address = 0x0170 */
+ [0x124] = 0x01,
+ [0x126] = 0x07, /* Address block length = 8 */
+ [0x128] = 0x76, /* Field 2 address = 0x0376 */
+ [0x12a] = 0x03,
+ [0x12c] = 0x01, /* Address block length = 2 */
+ [0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
+ [0x130] = 0x20, /* TPCE_MI = support power down mode */
+
+ [0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
+ [0x134] = 0x06, /* Tuple length = 6 bytes */
+ [0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */
+ [0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
+ [0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
+ [0x13c] = 0xb5, /* NomV: 3.3 V */
+ [0x13e] = 0x1e,
+ [0x140] = 0x3e, /* Peakl: 350 mA */
+
+ [0x142] = CISTPL_NO_LINK, /* No Link */
+ [0x144] = 0x00, /* Tuple length = 0 bytes */
+
+ [0x146] = CISTPL_END, /* Tuple End */
+};
+
+static int dscm1xxxx_attach(void *opaque)
+{
+ MicroDriveState *md = (MicroDriveState *) opaque;
+ md->card.attr_read = md_attr_read;
+ md->card.attr_write = md_attr_write;
+ md->card.common_read = md_common_read;
+ md->card.common_write = md_common_write;
+ md->card.io_read = md_common_read;
+ md->card.io_write = md_common_write;
+
+ md->attr_base = md->card.cis[0x74] | (md->card.cis[0x76] << 8);
+ md->io_base = 0x0;
+
+ md_reset(md);
+ md_interrupt_update(md);
+
+ md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
+ return 0;
+}
+
+static int dscm1xxxx_detach(void *opaque)
+{
+ MicroDriveState *md = (MicroDriveState *) opaque;
+ md_reset(md);
+ return 0;
+}
+
+PCMCIACardState *dscm1xxxx_init(BlockDriverState *bdrv)
+{
+ MicroDriveState *md = (MicroDriveState *) qemu_mallocz(sizeof(MicroDriveState));
+ md->card.state = md;
+ md->card.attach = dscm1xxxx_attach;
+ md->card.detach = dscm1xxxx_detach;
+ md->card.cis = dscm1xxxx_cis;
+ md->card.cis_len = sizeof(dscm1xxxx_cis);
+
+ ide_init2(&md->bus, bdrv, NULL, qemu_allocate_irqs(md_set_irq, md, 1)[0]);
+ md->bus.ifs[0].is_cf = 1;
+ md->bus.ifs[0].mdata_size = METADATA_SIZE;
+ md->bus.ifs[0].mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);
+
+ register_savevm("microdrive", -1, 3, md_save, md_load, md);
+
+ return &md->card;
+}
diff --git a/hw/ide.c b/hw/ide.c
index 01566ac..ea2165c 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -26,7 +26,6 @@
#include "pc.h"
#include "pci.h"
#include "scsi-disk.h"
-#include "pcmcia.h"
#include "block.h"
#include "block_int.h"
#include "qemu-timer.h"
@@ -2524,544 +2523,3 @@ void ide_dma_cancel(BMDMAState *bm)
}
}
-/***********************************************************/
-/* CF-ATA Microdrive */
-
-#define METADATA_SIZE 0x20
-
-/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
-typedef struct {
- IDEBus bus;
- PCMCIACardState card;
- uint32_t attr_base;
- uint32_t io_base;
-
- /* Card state */
- uint8_t opt;
- uint8_t stat;
- uint8_t pins;
-
- uint8_t ctrl;
- uint16_t io;
- int cycle;
-} MicroDriveState;
-
-/* Register bitfields */
-enum md_opt {
- OPT_MODE_MMAP = 0,
- OPT_MODE_IOMAP16 = 1,
- OPT_MODE_IOMAP1 = 2,
- OPT_MODE_IOMAP2 = 3,
- OPT_MODE = 0x3f,
- OPT_LEVIREQ = 0x40,
- OPT_SRESET = 0x80,
-};
-enum md_cstat {
- STAT_INT = 0x02,
- STAT_PWRDWN = 0x04,
- STAT_XE = 0x10,
- STAT_IOIS8 = 0x20,
- STAT_SIGCHG = 0x40,
- STAT_CHANGED = 0x80,
-};
-enum md_pins {
- PINS_MRDY = 0x02,
- PINS_CRDY = 0x20,
-};
-enum md_ctrl {
- CTRL_IEN = 0x02,
- CTRL_SRST = 0x04,
-};
-
-static inline void md_interrupt_update(MicroDriveState *s)
-{
- if (!s->card.slot)
- return;
-
- qemu_set_irq(s->card.slot->irq,
- !(s->stat & STAT_INT) && /* Inverted */
- !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
- !(s->opt & OPT_SRESET));
-}
-
-static void md_set_irq(void *opaque, int irq, int level)
-{
- MicroDriveState *s = (MicroDriveState *) opaque;
- if (level)
- s->stat |= STAT_INT;
- else
- s->stat &= ~STAT_INT;
-
- md_interrupt_update(s);
-}
-
-static void md_reset(MicroDriveState *s)
-{
- s->opt = OPT_MODE_MMAP;
- s->stat = 0;
- s->pins = 0;
- s->cycle = 0;
- s->ctrl = 0;
- ide_reset(s->bus.ifs);
-}
-
-static uint8_t md_attr_read(void *opaque, uint32_t at)
-{
- MicroDriveState *s = (MicroDriveState *) opaque;
- if (at < s->attr_base) {
- if (at < s->card.cis_len)
- return s->card.cis[at];
- else
- return 0x00;
- }
-
- at -= s->attr_base;
-
- switch (at) {
- case 0x00: /* Configuration Option Register */
- return s->opt;
- case 0x02: /* Card Configuration Status Register */
- if (s->ctrl & CTRL_IEN)
- return s->stat & ~STAT_INT;
- else
- return s->stat;
- case 0x04: /* Pin Replacement Register */
- return (s->pins & PINS_CRDY) | 0x0c;
- case 0x06: /* Socket and Copy Register */
- return 0x00;
-#ifdef VERBOSE
- default:
- printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
-#endif
- }
-
- return 0;
-}
-
-static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
-{
- MicroDriveState *s = (MicroDriveState *) opaque;
- at -= s->attr_base;
-
- switch (at) {
- case 0x00: /* Configuration Option Register */
- s->opt = value & 0xcf;
- if (value & OPT_SRESET)
- md_reset(s);
- md_interrupt_update(s);
- break;
- case 0x02: /* Card Configuration Status Register */
- if ((s->stat ^ value) & STAT_PWRDWN)
- s->pins |= PINS_CRDY;
- s->stat &= 0x82;
- s->stat |= value & 0x74;
- md_interrupt_update(s);
- /* Word 170 in Identify Device must be equal to STAT_XE */
- break;
- case 0x04: /* Pin Replacement Register */
- s->pins &= PINS_CRDY;
- s->pins |= value & PINS_MRDY;
- break;
- case 0x06: /* Socket and Copy Register */
- break;
- default:
- printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
- }
-}
-
-static uint16_t md_common_read(void *opaque, uint32_t at)
-{
- MicroDriveState *s = (MicroDriveState *) opaque;
- IDEState *ifs;
- uint16_t ret;
- at -= s->io_base;
-
- switch (s->opt & OPT_MODE) {
- case OPT_MODE_MMAP:
- if ((at & ~0x3ff) == 0x400)
- at = 0;
- break;
- case OPT_MODE_IOMAP16:
- at &= 0xf;
- break;
- case OPT_MODE_IOMAP1:
- if ((at & ~0xf) == 0x3f0)
- at -= 0x3e8;
- else if ((at & ~0xf) == 0x1f0)
- at -= 0x1f0;
- break;
- case OPT_MODE_IOMAP2:
- if ((at & ~0xf) == 0x370)
- at -= 0x368;
- else if ((at & ~0xf) == 0x170)
- at -= 0x170;
- }
-
- switch (at) {
- case 0x0: /* Even RD Data */
- case 0x8:
- return ide_data_readw(&s->bus, 0);
-
- /* TODO: 8-bit accesses */
- if (s->cycle)
- ret = s->io >> 8;
- else {
- s->io = ide_data_readw(&s->bus, 0);
- ret = s->io & 0xff;
- }
- s->cycle = !s->cycle;
- return ret;
- case 0x9: /* Odd RD Data */
- return s->io >> 8;
- case 0xd: /* Error */
- return ide_ioport_read(&s->bus, 0x1);
- case 0xe: /* Alternate Status */
- ifs = idebus_active_if(&s->bus);
- if (ifs->bs)
- return ifs->status;
- else
- return 0;
- case 0xf: /* Device Address */
- ifs = idebus_active_if(&s->bus);
- return 0xc2 | ((~ifs->select << 2) & 0x3c);
- default:
- return ide_ioport_read(&s->bus, at);
- }
-
- return 0;
-}
-
-static void md_common_write(void *opaque, uint32_t at, uint16_t value)
-{
- MicroDriveState *s = (MicroDriveState *) opaque;
- at -= s->io_base;
-
- switch (s->opt & OPT_MODE) {
- case OPT_MODE_MMAP:
- if ((at & ~0x3ff) == 0x400)
- at = 0;
- break;
- case OPT_MODE_IOMAP16:
- at &= 0xf;
- break;
- case OPT_MODE_IOMAP1:
- if ((at & ~0xf) == 0x3f0)
- at -= 0x3e8;
- else if ((at & ~0xf) == 0x1f0)
- at -= 0x1f0;
- break;
- case OPT_MODE_IOMAP2:
- if ((at & ~0xf) == 0x370)
- at -= 0x368;
- else if ((at & ~0xf) == 0x170)
- at -= 0x170;
- }
-
- switch (at) {
- case 0x0: /* Even WR Data */
- case 0x8:
- ide_data_writew(&s->bus, 0, value);
- break;
-
- /* TODO: 8-bit accesses */
- if (s->cycle)
- ide_data_writew(&s->bus, 0, s->io | (value << 8));
- else
- s->io = value & 0xff;
- s->cycle = !s->cycle;
- break;
- case 0x9:
- s->io = value & 0xff;
- s->cycle = !s->cycle;
- break;
- case 0xd: /* Features */
- ide_ioport_write(&s->bus, 0x1, value);
- break;
- case 0xe: /* Device Control */
- s->ctrl = value;
- if (value & CTRL_SRST)
- md_reset(s);
- md_interrupt_update(s);
- break;
- default:
- if (s->stat & STAT_PWRDWN) {
- s->pins |= PINS_CRDY;
- s->stat &= ~STAT_PWRDWN;
- }
- ide_ioport_write(&s->bus, at, value);
- }
-}
-
-static void md_save(QEMUFile *f, void *opaque)
-{
- MicroDriveState *s = (MicroDriveState *) opaque;
- int i;
-
- qemu_put_8s(f, &s->opt);
- qemu_put_8s(f, &s->stat);
- qemu_put_8s(f, &s->pins);
-
- qemu_put_8s(f, &s->ctrl);
- qemu_put_be16s(f, &s->io);
- qemu_put_byte(f, s->cycle);
-
- idebus_save(f, &s->bus);
-
- for (i = 0; i < 2; i ++)
- ide_save(f, &s->bus.ifs[i]);
-}
-
-static int md_load(QEMUFile *f, void *opaque, int version_id)
-{
- MicroDriveState *s = (MicroDriveState *) opaque;
- int i;
-
- if (version_id != 0 && version_id != 3)
- return -EINVAL;
-
- qemu_get_8s(f, &s->opt);
- qemu_get_8s(f, &s->stat);
- qemu_get_8s(f, &s->pins);
-
- qemu_get_8s(f, &s->ctrl);
- qemu_get_be16s(f, &s->io);
- s->cycle = qemu_get_byte(f);
-
- idebus_load(f, &s->bus, version_id);
-
- for (i = 0; i < 2; i ++)
- ide_load(f, &s->bus.ifs[i], version_id);
-
- return 0;
-}
-
-static const uint8_t dscm1xxxx_cis[0x14a] = {
- [0x000] = CISTPL_DEVICE, /* 5V Device Information */
- [0x002] = 0x03, /* Tuple length = 4 bytes */
- [0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
- [0x006] = 0x01, /* Size = 2K bytes */
- [0x008] = CISTPL_ENDMARK,
-
- [0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */
- [0x00c] = 0x04, /* Tuple length = 4 byest */
- [0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
- [0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
- [0x012] = 0x01, /* Size = 2K bytes */
- [0x014] = CISTPL_ENDMARK,
-
- [0x016] = CISTPL_JEDEC_C, /* JEDEC ID */
- [0x018] = 0x02, /* Tuple length = 2 bytes */
- [0x01a] = 0xdf, /* PC Card ATA with no Vpp required */
- [0x01c] = 0x01,
-
- [0x01e] = CISTPL_MANFID, /* Manufacture ID */
- [0x020] = 0x04, /* Tuple length = 4 bytes */
- [0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */
- [0x024] = 0x00,
- [0x026] = 0x00, /* PLMID_CARD = 0000 */
- [0x028] = 0x00,
-
- [0x02a] = CISTPL_VERS_1, /* Level 1 Version */
- [0x02c] = 0x12, /* Tuple length = 23 bytes */
- [0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
- [0x030] = 0x01, /* Minor Version = 1 */
- [0x032] = 'I',
- [0x034] = 'B',
- [0x036] = 'M',
- [0x038] = 0x00,
- [0x03a] = 'm',
- [0x03c] = 'i',
- [0x03e] = 'c',
- [0x040] = 'r',
- [0x042] = 'o',
- [0x044] = 'd',
- [0x046] = 'r',
- [0x048] = 'i',
- [0x04a] = 'v',
- [0x04c] = 'e',
- [0x04e] = 0x00,
- [0x050] = CISTPL_ENDMARK,
-
- [0x052] = CISTPL_FUNCID, /* Function ID */
- [0x054] = 0x02, /* Tuple length = 2 bytes */
- [0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */
- [0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
-
- [0x05a] = CISTPL_FUNCE, /* Function Extension */
- [0x05c] = 0x02, /* Tuple length = 2 bytes */
- [0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */
- [0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */
-
- [0x062] = CISTPL_FUNCE, /* Function Extension */
- [0x064] = 0x03, /* Tuple length = 3 bytes */
- [0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */
- [0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */
- [0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
-
- [0x06c] = CISTPL_CONFIG, /* Configuration */
- [0x06e] = 0x05, /* Tuple length = 5 bytes */
- [0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
- [0x072] = 0x07, /* TPCC_LAST = 7 */
- [0x074] = 0x00, /* TPCC_RADR = 0200 */
- [0x076] = 0x02,
- [0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */
-
- [0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
- [0x07c] = 0x0b, /* Tuple length = 11 bytes */
- [0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */
- [0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */
- [0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
- [0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
- [0x086] = 0x55, /* NomV: 5.0 V */
- [0x088] = 0x4d, /* MinV: 4.5 V */
- [0x08a] = 0x5d, /* MaxV: 5.5 V */
- [0x08c] = 0x4e, /* Peakl: 450 mA */
- [0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */
- [0x090] = 0x00, /* Window descriptor: Window length = 0 */
- [0x092] = 0x20, /* TPCE_MI: support power down mode, RW */
-
- [0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
- [0x096] = 0x06, /* Tuple length = 6 bytes */
- [0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */
- [0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
- [0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
- [0x09e] = 0xb5, /* NomV: 3.3 V */
- [0x0a0] = 0x1e,
- [0x0a2] = 0x3e, /* Peakl: 350 mA */
-
- [0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
- [0x0a6] = 0x0d, /* Tuple length = 13 bytes */
- [0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */
- [0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
- [0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
- [0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
- [0x0b0] = 0x55, /* NomV: 5.0 V */
- [0x0b2] = 0x4d, /* MinV: 4.5 V */
- [0x0b4] = 0x5d, /* MaxV: 5.5 V */
- [0x0b6] = 0x4e, /* Peakl: 450 mA */
- [0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */
- [0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */
- [0x0bc] = 0xff, /* IRQ0..IRQ7 supported */
- [0x0be] = 0xff, /* IRQ8..IRQ15 supported */
- [0x0c0] = 0x20, /* TPCE_MI = support power down mode */
-
- [0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
- [0x0c4] = 0x06, /* Tuple length = 6 bytes */
- [0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */
- [0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
- [0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
- [0x0cc] = 0xb5, /* NomV: 3.3 V */
- [0x0ce] = 0x1e,
- [0x0d0] = 0x3e, /* Peakl: 350 mA */
-
- [0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
- [0x0d4] = 0x12, /* Tuple length = 18 bytes */
- [0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */
- [0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
- [0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
- [0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
- [0x0de] = 0x55, /* NomV: 5.0 V */
- [0x0e0] = 0x4d, /* MinV: 4.5 V */
- [0x0e2] = 0x5d, /* MaxV: 5.5 V */
- [0x0e4] = 0x4e, /* Peakl: 450 mA */
- [0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
- [0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */
- [0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */
- [0x0ec] = 0x01,
- [0x0ee] = 0x07, /* Address block length = 8 */
- [0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */
- [0x0f2] = 0x03,
- [0x0f4] = 0x01, /* Address block length = 2 */
- [0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
- [0x0f8] = 0x20, /* TPCE_MI = support power down mode */
-
- [0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
- [0x0fc] = 0x06, /* Tuple length = 6 bytes */
- [0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */
- [0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
- [0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
- [0x104] = 0xb5, /* NomV: 3.3 V */
- [0x106] = 0x1e,
- [0x108] = 0x3e, /* Peakl: 350 mA */
-
- [0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
- [0x10c] = 0x12, /* Tuple length = 18 bytes */
- [0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */
- [0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
- [0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
- [0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
- [0x116] = 0x55, /* NomV: 5.0 V */
- [0x118] = 0x4d, /* MinV: 4.5 V */
- [0x11a] = 0x5d, /* MaxV: 5.5 V */
- [0x11c] = 0x4e, /* Peakl: 450 mA */
- [0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
- [0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */
- [0x122] = 0x70, /* Field 1 address = 0x0170 */
- [0x124] = 0x01,
- [0x126] = 0x07, /* Address block length = 8 */
- [0x128] = 0x76, /* Field 2 address = 0x0376 */
- [0x12a] = 0x03,
- [0x12c] = 0x01, /* Address block length = 2 */
- [0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
- [0x130] = 0x20, /* TPCE_MI = support power down mode */
-
- [0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
- [0x134] = 0x06, /* Tuple length = 6 bytes */
- [0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */
- [0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
- [0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
- [0x13c] = 0xb5, /* NomV: 3.3 V */
- [0x13e] = 0x1e,
- [0x140] = 0x3e, /* Peakl: 350 mA */
-
- [0x142] = CISTPL_NO_LINK, /* No Link */
- [0x144] = 0x00, /* Tuple length = 0 bytes */
-
- [0x146] = CISTPL_END, /* Tuple End */
-};
-
-static int dscm1xxxx_attach(void *opaque)
-{
- MicroDriveState *md = (MicroDriveState *) opaque;
- md->card.attr_read = md_attr_read;
- md->card.attr_write = md_attr_write;
- md->card.common_read = md_common_read;
- md->card.common_write = md_common_write;
- md->card.io_read = md_common_read;
- md->card.io_write = md_common_write;
-
- md->attr_base = md->card.cis[0x74] | (md->card.cis[0x76] << 8);
- md->io_base = 0x0;
-
- md_reset(md);
- md_interrupt_update(md);
-
- md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
- return 0;
-}
-
-static int dscm1xxxx_detach(void *opaque)
-{
- MicroDriveState *md = (MicroDriveState *) opaque;
- md_reset(md);
- return 0;
-}
-
-PCMCIACardState *dscm1xxxx_init(BlockDriverState *bdrv)
-{
- MicroDriveState *md = (MicroDriveState *) qemu_mallocz(sizeof(MicroDriveState));
- md->card.state = md;
- md->card.attach = dscm1xxxx_attach;
- md->card.detach = dscm1xxxx_detach;
- md->card.cis = dscm1xxxx_cis;
- md->card.cis_len = sizeof(dscm1xxxx_cis);
-
- ide_init2(&md->bus, bdrv, NULL, qemu_allocate_irqs(md_set_irq, md, 1)[0]);
- md->bus.ifs[0].is_cf = 1;
- md->bus.ifs[0].mdata_size = METADATA_SIZE;
- md->bus.ifs[0].mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);
-
- register_savevm("microdrive", -1, 3, md_save, md_load, md);
-
- return &md->card;
-}
--
1.6.2.5
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH 0/8] ide: cleanup and splitting.
2009-08-18 16:06 [Qemu-devel] [PATCH 0/8] ide: cleanup and splitting Gerd Hoffmann
` (7 preceding siblings ...)
2009-08-18 16:06 ` [Qemu-devel] [PATCH 8/8] ide: split away ide-microdrive.c Gerd Hoffmann
@ 2009-08-18 17:08 ` Avi Kivity
2009-08-19 6:37 ` Gerd Hoffmann
8 siblings, 1 reply; 15+ messages in thread
From: Avi Kivity @ 2009-08-18 17:08 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: qemu-devel
On 08/18/2009 07:06 PM, Gerd Hoffmann wrote:
> Hi,
>
> In preparation for qdev-ifying ide:
>
> Here is a patch series which cleaning up the ide code and splits it
> into multiple source files. The ide.c monster is cut down to roughtly
> half size after applying them ;)
>
>
Given that ide will likely grow, how about hw/ide/?
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 15+ messages in thread