From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MdlVZ-0005Vj-4g for qemu-devel@nongnu.org; Wed, 19 Aug 2009 09:47:21 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MdlVU-0005Qw-EW for qemu-devel@nongnu.org; Wed, 19 Aug 2009 09:47:20 -0400 Received: from [199.232.76.173] (port=55348 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MdlVU-0005Qc-2V for qemu-devel@nongnu.org; Wed, 19 Aug 2009 09:47:16 -0400 Received: from tx2ehsobe005.messaging.microsoft.com ([65.55.88.15]:44466 helo=TX2EHSOBE009.bigfish.com) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_ARCFOUR_MD5:16) (Exim 4.60) (envelope-from ) id 1MdlVT-0001zO-Lc for qemu-devel@nongnu.org; Wed, 19 Aug 2009 09:47:15 -0400 From: Andre Przywara Date: Wed, 19 Aug 2009 15:42:42 +0200 Message-ID: <1250689362-11067-4-git-send-email-andre.przywara@amd.com> In-Reply-To: <1250689362-11067-1-git-send-email-andre.przywara@amd.com> References: <1250689362-11067-1-git-send-email-andre.przywara@amd.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 3/3] set CPUID bits to present cores and threads topology List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: anthony@codemonkey.ws Cc: Andre Przywara , qemu-devel@nongnu.org Controlled by the enhanced -smp option set the CPUID bits to present the guest the desired topology. This is vendor specific, but (with the exception of the CMP_LEGACY bit) not conflicting, so we set all bits everytime. There is no real multithreading support for AMD CPUs, so report cores instead. Signed-off-by: Andre Przywara --- target-i386/helper.c | 28 +++++++++++++++++++++++++--- 1 files changed, 25 insertions(+), 3 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index 7de4c07..d4dfcbd 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1631,6 +1631,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ *ecx = env->cpuid_ext_features; *edx = env->cpuid_features; + if (env->nr_cores * env->nr_threads > 1) { + *ebx |= (env->nr_cores * env->nr_threads) << 16; + *edx |= 1 << 28; /* HTT bit */ + } break; case 2: /* cache info: needed for Pentium Pro compatibility */ @@ -1641,21 +1645,29 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 4: /* cache info: needed for Core compatibility */ + if (env->nr_cores > 1) { + *eax = (env->nr_cores - 1) << 26; + } else { + *eax = 0; + } switch (count) { case 0: /* L1 dcache info */ - *eax = 0x0000121; + *eax |= 0x0000121; *ebx = 0x1c0003f; *ecx = 0x000003f; *edx = 0x0000001; break; case 1: /* L1 icache info */ - *eax = 0x0000122; + *eax |= 0x0000122; *ebx = 0x1c0003f; *ecx = 0x000003f; *edx = 0x0000001; break; case 2: /* L2 cache info */ - *eax = 0x0000143; + *eax |= 0x0000143; + if (env->nr_threads > 1) { + *eax |= (env->nr_threads - 1) << 14; + } *ebx = 0x3c0003f; *ecx = 0x0000fff; *edx = 0x0000001; @@ -1708,6 +1720,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ecx = env->cpuid_ext3_features; *edx = env->cpuid_ext2_features; + if (env->nr_cores * env->nr_threads > 1 && + env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && + env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && + env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) { + *ecx |= 1 << 1; /* CmpLegacy bit */ + } + if (kvm_enabled()) { /* Nested SVM not yet supported in KVM */ *ecx &= ~CPUID_EXT3_SVM; @@ -1762,6 +1781,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ebx = 0; *ecx = 0; *edx = 0; + if (env->nr_cores * env->nr_threads > 1) { + *ecx |= (env->nr_cores * env->nr_threads) - 1; + } break; case 0x8000000A: *eax = 0x00000001; /* SVM Revision */ -- 1.6.1.3