From: Miles Glenn <milesg@linux.ibm.com>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, "Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Michael Kowal" <kowal@linux.ibm.com>,
"Caleb Schlossin" <calebs@linux.vnet.ibm.com>
Subject: Re: [PATCH 12/50] ppc/xive2: Set CPPR delivery should account for group priority
Date: Thu, 15 May 2025 10:45:26 -0500 [thread overview]
Message-ID: <12549968b1d9a0a89b32900b3fc8c4a574a28906.camel@linux.ibm.com> (raw)
In-Reply-To: <20250512031100.439842-13-npiggin@gmail.com>
On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote:
> The group interrupt delivery flow selects the group backlog scan if
> LSMFB < IPB, but that scan may find an interrupt with a priority >=
> IPB. In that case, the VP-direct interrupt should be chosen. This
> extends to selecting the lowest prio between POOL and PHYS rings.
>
> Implement this just by re-starting the selection logic if the
> backlog irq was not found or priority did not match LSMFB (LSMFB
> is updated so next time around it would see the right value and
> not loop infinitely).
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> hw/intc/xive2.c | 32 ++++++++++++++++++++++----------
> 1 file changed, 22 insertions(+), 10 deletions(-)
>
> diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
> index 8ede95b671..de139dcfbf 100644
> --- a/hw/intc/xive2.c
> +++ b/hw/intc/xive2.c
> @@ -939,7 +939,7 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
> {
> uint8_t *regs = &tctx->regs[ring];
> Xive2Router *xrtr = XIVE2_ROUTER(tctx->xptr);
> - uint8_t old_cppr, backlog_prio, first_group, group_level = 0;
> + uint8_t old_cppr, backlog_prio, first_group, group_level;
> uint8_t pipr_min, lsmfb_min, ring_min;
> bool group_enabled;
> uint32_t nvp_blk, nvp_idx;
> @@ -961,10 +961,12 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
> * Recompute the PIPR based on local pending interrupts. It will
> * be adjusted below if needed in case of pending group interrupts.
> */
> +again:
> pipr_min = xive_ipb_to_pipr(regs[TM_IPB]);
> group_enabled = !!regs[TM_LGS];
> - lsmfb_min = (group_enabled) ? regs[TM_LSMFB] : 0xff;
> + lsmfb_min = group_enabled ? regs[TM_LSMFB] : 0xff;
> ring_min = ring;
> + group_level = 0;
>
> /* PHYS updates also depend on POOL values */
> if (ring == TM_QW3_HV_PHYS) {
> @@ -998,9 +1000,6 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
> }
> }
>
> - /* PIPR should not be set to a value greater than CPPR */
> - regs[TM_PIPR] = (pipr_min > cppr) ? cppr : pipr_min;
> -
> rc = xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx);
> if (rc) {
> qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid context\n");
> @@ -1019,7 +1018,7 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
>
> if (group_enabled &&
> lsmfb_min < cppr &&
> - lsmfb_min < regs[TM_PIPR]) {
> + lsmfb_min < pipr_min) {
> /*
> * Thread has seen a group interrupt with a higher priority
> * than the new cppr or pending local interrupt. Check the
> @@ -1048,12 +1047,25 @@ static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
> nvp_blk, nvp_idx,
> first_group, &group_level);
> tctx->regs[ring_min + TM_LSMFB] = backlog_prio;
> - if (backlog_prio != 0xFF) {
> - xive2_presenter_backlog_decr(tctx->xptr, nvp_blk, nvp_idx,
> - backlog_prio, group_level);
> - regs[TM_PIPR] = backlog_prio;
> + if (backlog_prio != lsmfb_min) {
> + /*
> + * If the group backlog scan finds a less favored or no interrupt,
> + * then re-do the processing which may turn up a more favored
> + * interrupt from IPB or the other pool. Backlog should not
> + * find a priority < LSMFB.
> + */
> + g_assert(backlog_prio >= lsmfb_min);
> + goto again;
> }
> +
> + xive2_presenter_backlog_decr(tctx->xptr, nvp_blk, nvp_idx,
> + backlog_prio, group_level);
> + pipr_min = backlog_prio;
> }
> +
> + /* PIPR should not be set to a value greater than CPPR */
> + regs[TM_PIPR] = (pipr_min > cppr) ? cppr : pipr_min;
> +
> /* CPPR has changed, check if we need to raise a pending exception */
> xive_tctx_notify(tctx, ring_min, group_level);
> }
next prev parent reply other threads:[~2025-05-15 15:48 UTC|newest]
Thread overview: 192+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-12 3:10 [PATCH 00/50] ppc/xive: updates for PowerVM Nicholas Piggin
2025-05-12 3:10 ` [PATCH 01/50] ppc/xive: Fix xive trace event output Nicholas Piggin
2025-05-14 14:26 ` Caleb Schlossin
2025-05-14 18:41 ` Mike Kowal
2025-05-15 15:30 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 02/50] ppc/xive: Report access size in XIVE TM operation error logs Nicholas Piggin
2025-05-14 14:27 ` Caleb Schlossin
2025-05-14 18:42 ` Mike Kowal
2025-05-15 15:31 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 03/50] ppc/xive2: Fix calculation of END queue sizes Nicholas Piggin
2025-05-14 14:27 ` Caleb Schlossin
2025-05-14 18:45 ` Mike Kowal
2025-05-16 0:06 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 04/50] ppc/xive2: Remote VSDs need to match on forwarding address Nicholas Piggin
2025-05-14 14:27 ` Caleb Schlossin
2025-05-14 18:46 ` Mike Kowal
2025-05-15 15:34 ` Miles Glenn
2025-05-16 0:08 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 05/50] ppc/xive2: fix context push calculation of IPB priority Nicholas Piggin
2025-05-14 14:30 ` Caleb Schlossin
2025-05-14 18:48 ` Mike Kowal
2025-05-15 15:36 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 06/50] ppc/xive: Fix PHYS NSR ring matching Nicholas Piggin
2025-05-14 14:30 ` Caleb Schlossin
2025-05-14 18:49 ` Mike Kowal
2025-05-15 15:39 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 07/50] ppc/xive2: Reset Generation Flipped bit on END Cache Watch Nicholas Piggin
2025-05-14 14:30 ` Caleb Schlossin
2025-05-14 18:50 ` Mike Kowal
2025-05-15 15:41 ` Miles Glenn
2025-05-16 0:09 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 08/50] ppc/xive2: Use fair irq target search algorithm Nicholas Piggin
2025-05-14 14:31 ` Caleb Schlossin
2025-05-14 18:51 ` Mike Kowal
2025-05-15 15:42 ` Miles Glenn
2025-05-16 0:12 ` Nicholas Piggin
2025-05-16 16:22 ` Mike Kowal
2025-05-12 3:10 ` [PATCH 09/50] ppc/xive2: Fix irq preempted by lower priority group irq Nicholas Piggin
2025-05-14 14:31 ` Caleb Schlossin
2025-05-14 18:52 ` Mike Kowal
2025-05-16 0:12 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 10/50] ppc/xive2: Fix treatment of PIPR in CPPR update Nicholas Piggin
2025-05-14 14:32 ` Caleb Schlossin
2025-05-14 18:53 ` Mike Kowal
2025-05-16 0:15 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 11/50] ppc/xive2: Do not present group interrupt on OS-push if precluded by CPPR Nicholas Piggin
2025-05-14 14:32 ` Caleb Schlossin
2025-05-14 18:54 ` Mike Kowal
2025-05-15 15:43 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 12/50] ppc/xive2: Set CPPR delivery should account for group priority Nicholas Piggin
2025-05-14 14:33 ` Caleb Schlossin
2025-05-14 18:57 ` Mike Kowal
2025-05-15 15:45 ` Miles Glenn [this message]
2025-05-12 3:10 ` [PATCH 13/50] ppc/xive: tctx_notify should clear the precluded interrupt Nicholas Piggin
2025-05-14 14:33 ` Caleb Schlossin
2025-05-14 18:58 ` Mike Kowal
2025-05-15 15:46 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 14/50] ppc/xive: Explicitly zero NSR after accepting Nicholas Piggin
2025-05-14 14:34 ` Caleb Schlossin
2025-05-14 19:07 ` Mike Kowal
2025-05-15 23:31 ` Nicholas Piggin
2025-05-15 15:47 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 15/50] ppc/xive: Move NSR decoding into helper functions Nicholas Piggin
2025-05-14 14:35 ` Caleb Schlossin
2025-05-14 19:04 ` Mike Kowal
2025-05-15 15:48 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 16/50] ppc/xive: Fix pulling pool and phys contexts Nicholas Piggin
2025-05-14 14:36 ` Caleb Schlossin
2025-05-14 19:01 ` Mike Kowal
2025-05-15 15:49 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 17/50] pnv/xive2: Support ESB Escalation Nicholas Piggin
2025-05-14 14:36 ` Caleb Schlossin
2025-05-14 19:00 ` Mike Kowal
2025-05-16 0:05 ` Nicholas Piggin
2025-05-16 15:44 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 18/50] pnv/xive2: Print value in invalid register write logging Nicholas Piggin
2025-05-14 14:36 ` Caleb Schlossin
2025-05-14 19:09 ` Mike Kowal
2025-05-15 15:50 ` Miles Glenn
2025-05-16 0:15 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 19/50] pnv/xive2: VC_ENDC_WATCH_SPEC regs should read back WATCH_FULL Nicholas Piggin
2025-05-14 14:37 ` Caleb Schlossin
2025-05-14 19:10 ` Mike Kowal
2025-05-15 15:51 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 20/50] pnv/xive2: Permit valid writes to VC/PC Flush Control registers Nicholas Piggin
2025-05-14 14:37 ` Caleb Schlossin
2025-05-14 19:11 ` Mike Kowal
2025-05-15 15:52 ` Miles Glenn
2025-05-16 0:18 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 21/50] ppc/xive2: add interrupt priority configuration flags Nicholas Piggin
2025-05-14 19:41 ` Mike Kowal
2025-05-16 0:18 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 22/50] ppc/xive2: Support redistribution of group interrupts Nicholas Piggin
2025-05-14 19:42 ` Mike Kowal
2025-05-16 0:19 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 23/50] ppc/xive: Add more interrupt notification tracing Nicholas Piggin
2025-05-14 19:46 ` Mike Kowal
2025-05-16 0:19 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 24/50] ppc/xive2: Improve pool regs variable name Nicholas Piggin
2025-05-14 19:47 ` Mike Kowal
2025-05-16 0:19 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 25/50] ppc/xive2: Implement "Ack OS IRQ to even report line" TIMA op Nicholas Piggin
2025-05-14 19:48 ` Mike Kowal
2025-05-16 0:20 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 26/50] ppc/xive2: Redistribute group interrupt precluded by CPPR update Nicholas Piggin
2025-05-14 19:48 ` Mike Kowal
2025-05-16 0:20 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 27/50] ppc/xive2: redistribute irqs for pool and phys ctx pull Nicholas Piggin
2025-05-14 19:51 ` Mike Kowal
2025-05-12 3:10 ` [PATCH 28/50] ppc/xive: Change presenter .match_nvt to match not present Nicholas Piggin
2025-05-14 19:54 ` Mike Kowal
2025-05-15 23:40 ` Nicholas Piggin
2025-05-15 15:53 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 29/50] ppc/xive2: Redistribute group interrupt preempted by higher priority interrupt Nicholas Piggin
2025-05-14 19:55 ` Mike Kowal
2025-05-15 15:54 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 30/50] ppc/xive: Add xive_tctx_pipr_present() to present new interrupt Nicholas Piggin
2025-05-14 20:10 ` Mike Kowal
2025-05-15 15:21 ` Mike Kowal
2025-05-15 23:51 ` Nicholas Piggin
2025-05-15 23:43 ` Nicholas Piggin
2025-05-15 15:55 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 31/50] ppc/xive: Fix high prio group interrupt being preempted by low prio VP Nicholas Piggin
2025-05-15 15:21 ` Mike Kowal
2025-05-15 15:55 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 32/50] ppc/xive: Split xive recompute from IPB function Nicholas Piggin
2025-05-14 20:42 ` Mike Kowal
2025-05-15 23:46 ` Nicholas Piggin
2025-05-15 15:56 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 33/50] ppc/xive: tctx signaling registers rework Nicholas Piggin
2025-05-14 20:49 ` Mike Kowal
2025-05-15 15:58 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 34/50] ppc/xive: tctx_accept only lower irq line if an interrupt was presented Nicholas Piggin
2025-05-15 15:16 ` Mike Kowal
2025-05-15 23:50 ` Nicholas Piggin
2025-05-15 16:04 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 35/50] ppc/xive: Add xive_tctx_pipr_set() helper function Nicholas Piggin
2025-05-15 15:18 ` Mike Kowal
2025-05-15 16:05 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 36/50] ppc/xive2: split tctx presentation processing from set CPPR Nicholas Piggin
2025-05-15 15:24 ` Mike Kowal
2025-05-15 16:06 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 37/50] ppc/xive2: Consolidate presentation processing in context push Nicholas Piggin
2025-05-15 15:25 ` Mike Kowal
2025-05-15 16:06 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 38/50] ppc/xive2: Avoid needless interrupt re-check on CPPR set Nicholas Piggin
2025-05-15 15:26 ` Mike Kowal
2025-05-15 16:07 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 39/50] ppc/xive: Assert group interrupts were redistributed Nicholas Piggin
2025-05-15 15:28 ` Mike Kowal
2025-05-15 16:08 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 40/50] ppc/xive2: implement NVP context save restore for POOL ring Nicholas Piggin
2025-05-15 15:36 ` Mike Kowal
2025-05-15 16:09 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 41/50] ppc/xive2: Prevent pulling of pool context losing phys interrupt Nicholas Piggin
2025-05-15 15:43 ` Mike Kowal
2025-05-15 16:10 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 42/50] ppc/xive: Redistribute phys after pulling of pool context Nicholas Piggin
2025-05-15 15:46 ` Mike Kowal
2025-05-15 16:11 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 43/50] ppc/xive: Check TIMA operations validity Nicholas Piggin
2025-05-15 15:47 ` Mike Kowal
2025-05-15 16:12 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 44/50] ppc/xive2: Implement pool context push TIMA op Nicholas Piggin
2025-05-15 15:48 ` Mike Kowal
2025-05-15 16:13 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 45/50] ppc/xive2: redistribute group interrupts on context push Nicholas Piggin
2025-05-15 15:44 ` Mike Kowal
2025-05-15 16:13 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 46/50] ppc/xive2: Implement set_os_pending TIMA op Nicholas Piggin
2025-05-15 15:49 ` Mike Kowal
2025-05-15 16:14 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 47/50] ppc/xive2: Implement POOL LGS push " Nicholas Piggin
2025-05-15 15:50 ` Mike Kowal
2025-05-15 16:15 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 48/50] ppc/xive2: Implement PHYS ring VP " Nicholas Piggin
2025-05-15 15:50 ` Mike Kowal
2025-05-15 16:16 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 49/50] ppc/xive: Split need_resend into restore_nvp Nicholas Piggin
2025-05-15 15:57 ` Mike Kowal
2025-05-15 16:16 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 50/50] ppc/xive2: Enable lower level contexts on VP push Nicholas Piggin
2025-05-15 15:54 ` Mike Kowal
2025-05-15 16:17 ` Miles Glenn
2025-05-15 15:36 ` [PATCH 00/50] ppc/xive: updates for PowerVM Cédric Le Goater
2025-05-16 1:29 ` Nicholas Piggin
2025-07-20 21:26 ` Cédric Le Goater
2025-08-04 17:37 ` Miles Glenn
2025-08-05 5:09 ` Cédric Le Goater
2025-08-05 15:52 ` Miles Glenn
2025-08-05 20:09 ` Cédric Le Goater
2025-07-03 9:37 ` Gautam Menghani
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