From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NCgHM-0005da-6y for qemu-devel@nongnu.org; Mon, 23 Nov 2009 16:17:00 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NCgHH-0005ah-0o for qemu-devel@nongnu.org; Mon, 23 Nov 2009 16:16:59 -0500 Received: from [199.232.76.173] (port=33125 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NCgHG-0005ab-RZ for qemu-devel@nongnu.org; Mon, 23 Nov 2009 16:16:54 -0500 Received: from mx20.gnu.org ([199.232.41.8]:28531) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NCgHG-0000Tx-Jy for qemu-devel@nongnu.org; Mon, 23 Nov 2009 16:16:54 -0500 Received: from mail.codesourcery.com ([38.113.113.100]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NCgHF-00015C-Am for qemu-devel@nongnu.org; Mon, 23 Nov 2009 16:16:53 -0500 From: Nathan Froyd Date: Mon, 23 Nov 2009 12:50:00 -0800 Message-Id: <1259009409-2755-3-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1259009409-2755-1-git-send-email-froydnj@codesourcery.com> References: <1259009409-2755-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 02/11] target-mips: add new HFLAGs for JALX and 16/32-bit delay slots List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org We create separate masks for the "basic" branch hflags and the "extended" branch hflags and define MIPS_HFLAG_BMASK as the logical or of those two. This is done to avoid churning the codebase in lots of different places. Signed-off-by: Nathan Froyd --- target-mips/cpu.h | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index e8febe6..9413be0 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -441,11 +441,17 @@ struct CPUMIPSState { * the delay slot, record what type of branch it is so that we can * resume translation properly. It might be possible to reduce * this from three bits to two. */ -#define MIPS_HFLAG_BMASK 0x1C00 +#define MIPS_HFLAG_BMASK_BASE 0x1C00 #define MIPS_HFLAG_B 0x0400 /* Unconditional branch */ #define MIPS_HFLAG_BC 0x0800 /* Conditional branch */ #define MIPS_HFLAG_BL 0x0C00 /* Likely branch */ #define MIPS_HFLAG_BR 0x1000 /* branch to register (can't link TB) */ + /* Extra flags about the current pending branch. */ +#define MIPS_HFLAG_BMASK_EXT 0xE000 +#define MIPS_HFLAG_BDS16 0x2000 /* branch requires 16-bit delay slot */ +#define MIPS_HFLAG_BDS32 0x4000 /* branch requires 32-bit delay slot */ +#define MIPS_HFLAG_BX 0x8000 /* branch exchange execution mode */ +#define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) target_ulong btarget; /* Jump / branch target */ target_ulong bcond; /* Branch condition (if needed) */ -- 1.6.3.2