From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NCfy0-0000Og-N8 for qemu-devel@nongnu.org; Mon, 23 Nov 2009 15:57:00 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NCfxv-0000Ep-4j for qemu-devel@nongnu.org; Mon, 23 Nov 2009 15:56:59 -0500 Received: from [199.232.76.173] (port=52533 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NCfxu-0000EI-PP for qemu-devel@nongnu.org; Mon, 23 Nov 2009 15:56:54 -0500 Received: from mx20.gnu.org ([199.232.41.8]:27845) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NCfxu-00069J-EQ for qemu-devel@nongnu.org; Mon, 23 Nov 2009 15:56:54 -0500 Received: from mail.codesourcery.com ([38.113.113.100]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NCfxt-0000FW-Lx for qemu-devel@nongnu.org; Mon, 23 Nov 2009 15:56:53 -0500 From: Nathan Froyd Date: Mon, 23 Nov 2009 12:50:01 -0800 Message-Id: <1259009409-2755-4-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1259009409-2755-1-git-send-email-froydnj@codesourcery.com> References: <1259009409-2755-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 03/11] target-mips: change interrupt bits to be mips16-aware List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Nathan Froyd --- target-mips/helper.c | 47 ++++++++++++++++++++++++++--------------------- target-mips/op_helper.c | 10 +++++++--- 2 files changed, 33 insertions(+), 24 deletions(-) diff --git a/target-mips/helper.c b/target-mips/helper.c index 4a37277..e54a31a 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -339,6 +339,20 @@ static const char * const excp_names[EXCP_LAST + 1] = { [EXCP_CACHE] = "cache error", }; +static target_ulong exception_resume_pc (CPUState *env) +{ + target_ulong bad_pc; + + bad_pc = env->active_tc.PC | env->active_tc.ISAMode; + if (env->hflags & MIPS_HFLAG_BMASK) { + /* If the exception was raised from a delay slot, come back to + the jump. */ + bad_pc -= (env->hflags & MIPS_HFLAG_BDS16 ? 2 : 4); + } + + return bad_pc; +} + void do_interrupt (CPUState *env) { #if !defined(CONFIG_USER_ONLY) @@ -366,7 +380,7 @@ void do_interrupt (CPUState *env) resume will always occur on the next instruction (but we assume the pc has always been updated during code translation). */ - env->CP0_DEPC = env->active_tc.PC; + env->CP0_DEPC = env->active_tc.PC | env->active_tc.ISAMode; goto enter_debug_mode; case EXCP_DINT: env->CP0_Debug |= 1 << CP0DB_DINT; @@ -383,14 +397,8 @@ void do_interrupt (CPUState *env) case EXCP_DDBL: env->CP0_Debug |= 1 << CP0DB_DDBL; set_DEPC: - if (env->hflags & MIPS_HFLAG_BMASK) { - /* If the exception was raised from a delay slot, - come back to the jump. */ - env->CP0_DEPC = env->active_tc.PC - 4; - env->hflags &= ~MIPS_HFLAG_BMASK; - } else { - env->CP0_DEPC = env->active_tc.PC; - } + env->CP0_DEPC = exception_resume_pc(env); + env->hflags &= ~MIPS_HFLAG_BMASK; enter_debug_mode: env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; env->hflags &= ~(MIPS_HFLAG_KSU); @@ -398,6 +406,8 @@ void do_interrupt (CPUState *env) if (!(env->CP0_Status & (1 << CP0St_EXL))) env->CP0_Cause &= ~(1 << CP0Ca_BD); env->active_tc.PC = (int32_t)0xBFC00480; + /* Exception handlers are entered in 32-bit mode. */ + env->active_tc.ISAMode = 0; break; case EXCP_RESET: cpu_reset(env); @@ -409,20 +419,16 @@ void do_interrupt (CPUState *env) case EXCP_NMI: env->CP0_Status |= (1 << CP0St_NMI); set_error_EPC: - if (env->hflags & MIPS_HFLAG_BMASK) { - /* If the exception was raised from a delay slot, - come back to the jump. */ - env->CP0_ErrorEPC = env->active_tc.PC - 4; - env->hflags &= ~MIPS_HFLAG_BMASK; - } else { - env->CP0_ErrorEPC = env->active_tc.PC; - } + env->CP0_ErrorEPC = exception_resume_pc(env); + env->hflags &= ~MIPS_HFLAG_BMASK; env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; env->hflags &= ~(MIPS_HFLAG_KSU); if (!(env->CP0_Status & (1 << CP0St_EXL))) env->CP0_Cause &= ~(1 << CP0Ca_BD); env->active_tc.PC = (int32_t)0xBFC00000; + /* Exception handlers are entered in 32-bit mode. */ + env->active_tc.ISAMode = 0; break; case EXCP_EXT_INTERRUPT: cause = 0; @@ -524,13 +530,10 @@ void do_interrupt (CPUState *env) } set_EPC: if (!(env->CP0_Status & (1 << CP0St_EXL))) { + env->CP0_EPC = exception_resume_pc(env); if (env->hflags & MIPS_HFLAG_BMASK) { - /* If the exception was raised from a delay slot, - come back to the jump. */ - env->CP0_EPC = env->active_tc.PC - 4; env->CP0_Cause |= (1 << CP0Ca_BD); } else { - env->CP0_EPC = env->active_tc.PC; env->CP0_Cause &= ~(1 << CP0Ca_BD); } env->CP0_Status |= (1 << CP0St_EXL); @@ -544,6 +547,8 @@ void do_interrupt (CPUState *env) env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); } env->active_tc.PC += offset; + /* Exception handlers are entered in 32-bit mode. */ + env->active_tc.ISAMode = 0; env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); break; default: diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 52d687d..d585d65 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1701,10 +1701,12 @@ void helper_eret (void) { debug_pre_eret(); if (env->CP0_Status & (1 << CP0St_ERL)) { - env->active_tc.PC = env->CP0_ErrorEPC; + env->active_tc.PC = env->CP0_ErrorEPC & ~(target_ulong)1; + env->active_tc.ISAMode = env->CP0_ErrorEPC & 1; env->CP0_Status &= ~(1 << CP0St_ERL); } else { - env->active_tc.PC = env->CP0_EPC; + env->active_tc.PC = env->CP0_EPC & ~(target_ulong)1; + env->active_tc.ISAMode = env->CP0_EPC & 1; env->CP0_Status &= ~(1 << CP0St_EXL); } compute_hflags(env); @@ -1715,7 +1717,9 @@ void helper_eret (void) void helper_deret (void) { debug_pre_eret(); - env->active_tc.PC = env->CP0_DEPC; + env->active_tc.PC = env->CP0_DEPC & ~(target_ulong)1; + env->active_tc.ISAMode = env->CP0_DEPC & 1; + env->hflags &= MIPS_HFLAG_DM; compute_hflags(env); debug_post_eret(); -- 1.6.3.2