From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NCqXK-0006Yr-3g for qemu-devel@nongnu.org; Tue, 24 Nov 2009 03:14:10 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NCqXF-0006Xx-48 for qemu-devel@nongnu.org; Tue, 24 Nov 2009 03:14:09 -0500 Received: from [199.232.76.173] (port=33006 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NCqXE-0006Xr-RE for qemu-devel@nongnu.org; Tue, 24 Nov 2009 03:14:04 -0500 Received: from mx20.gnu.org ([199.232.41.8]:60268) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NCqXE-0004WS-Bf for qemu-devel@nongnu.org; Tue, 24 Nov 2009 03:14:04 -0500 Received: from cantor.suse.de ([195.135.220.2] helo=mx1.suse.de) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NCqXD-0005ky-5n for qemu-devel@nongnu.org; Tue, 24 Nov 2009 03:14:03 -0500 From: Alexander Graf Date: Tue, 24 Nov 2009 09:01:52 +0100 Message-Id: <1259049712-8165-2-git-send-email-agraf@suse.de> In-Reply-To: <1259049712-8165-1-git-send-email-agraf@suse.de> References: <1259049712-8165-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH] PPC: Get MMU state on register sync List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org While x86 only needs to sync cr0-4 to know all about its MMU state and enable qemu to resolve virtual to physical addresses, we need to sync all of the segment registers on PPC to know which mapping we're in. So let's grab the segment register contents to be able to use the "x" monitor command and also enable the gdbstub to resolve virtual addresses. I sent the corresponding KVM patch to the KVM ML some minutes ago. Signed-off-by: Alexander Graf --- target-ppc/kvm.c | 30 ++++++++++++++++++++++++++++++ 1 files changed, 30 insertions(+), 0 deletions(-) diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 4e1c65f..566513f 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -98,12 +98,17 @@ int kvm_arch_put_registers(CPUState *env) int kvm_arch_get_registers(CPUState *env) { struct kvm_regs regs; + struct kvm_sregs sregs; uint32_t i, ret; ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); if (ret < 0) return ret; + ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); + if (ret < 0) + return ret; + env->ctr = regs.ctr; env->lr = regs.lr; env->xer = regs.xer; @@ -125,6 +130,31 @@ int kvm_arch_get_registers(CPUState *env) for (i = 0;i < 32; i++) env->gpr[i] = regs.gpr[i]; +#ifdef KVM_CAP_PPC_SEGSTATE + if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_SEGSTATE)) { + env->sdr1 = sregs.sdr1; + + /* Sync SLB */ + for (i = 0; i < 64; i++) { + ppc_store_slb(env, sregs.ppc64.slb[i].slbe, + sregs.ppc64.slb[i].slbv); + } + + /* Sync SRs */ + for (i = 0; i < 16; i++) { + env->sr[i] = sregs.ppc32.sr[i]; + } + + /* Sync BATs */ + for (i = 0; i < 8; i++) { + env->DBAT[0][i] = sregs.ppc32.dbat[i] & 0xffffffff; + env->DBAT[1][i] = sregs.ppc32.dbat[i] >> 32; + env->IBAT[0][i] = sregs.ppc32.ibat[i] & 0xffffffff; + env->IBAT[1][i] = sregs.ppc32.ibat[i] >> 32; + } + } +#endif + return 0; } -- 1.6.0.2