From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NI2kQ-0001sK-32 for qemu-devel@nongnu.org; Tue, 08 Dec 2009 11:17:10 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NI2kL-0001q0-Jp for qemu-devel@nongnu.org; Tue, 08 Dec 2009 11:17:09 -0500 Received: from [199.232.76.173] (port=40707 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NI2kL-0001pq-7K for qemu-devel@nongnu.org; Tue, 08 Dec 2009 11:17:05 -0500 Received: from mx20.gnu.org ([199.232.41.8]:51958) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NI2kK-0001VG-UR for qemu-devel@nongnu.org; Tue, 08 Dec 2009 11:17:05 -0500 Received: from mail.codesourcery.com ([38.113.113.100]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NI2kJ-0000ui-ST for qemu-devel@nongnu.org; Tue, 08 Dec 2009 11:17:04 -0500 From: Nathan Froyd Date: Tue, 8 Dec 2009 08:06:30 -0800 Message-Id: <1260288392-20804-10-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1260288392-20804-1-git-send-email-froydnj@codesourcery.com> References: <1260288392-20804-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 09/11] gdbstub: add MIPS16 support List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The only thing to do here is to expose the current processor mode to GDB and to set the processor mode properly when we change the PC. Signed-off-by: Nathan Froyd --- gdbstub.c | 18 +++++++++++++++--- 1 files changed, 15 insertions(+), 3 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 5320b1c..6180171 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1053,7 +1053,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) case 34: GET_REGL(env->active_tc.HI[0]); case 35: GET_REGL(env->CP0_BadVAddr); case 36: GET_REGL((int32_t)env->CP0_Cause); - case 37: GET_REGL(env->active_tc.PC); + case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16)); case 72: GET_REGL(0); /* fp */ case 89: GET_REGL((int32_t)env->CP0_PRid); } @@ -1114,7 +1114,14 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) case 34: env->active_tc.HI[0] = tmp; break; case 35: env->CP0_BadVAddr = tmp; break; case 36: env->CP0_Cause = tmp; break; - case 37: env->active_tc.PC = tmp; break; + case 37: + env->active_tc.PC = tmp & ~(target_ulong)1; + if (tmp & 1) { + env->hflags |= MIPS_HFLAG_M16; + } else { + env->hflags &= ~(MIPS_HFLAG_M16); + } + break; case 72: /* fp, ignored */ break; default: if (n > 89) @@ -1658,7 +1665,12 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc) #elif defined (TARGET_SH4) s->c_cpu->pc = pc; #elif defined (TARGET_MIPS) - s->c_cpu->active_tc.PC = pc; + s->c_cpu->active_tc.PC = pc & ~(target_ulong)1; + if (pc & 1) { + s->c_cpu->hflags |= MIPS_HFLAG_M16; + } else { + s->c_cpu->hflags &= ~(MIPS_HFLAG_M16); + } #elif defined (TARGET_MICROBLAZE) s->c_cpu->sregs[SR_PC] = pc; #elif defined (TARGET_CRIS) -- 1.6.3.2