From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NJ9J2-0005Sz-5q for qemu-devel@nongnu.org; Fri, 11 Dec 2009 12:29:28 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NJ9Ix-0005PU-FX for qemu-devel@nongnu.org; Fri, 11 Dec 2009 12:29:27 -0500 Received: from [199.232.76.173] (port=59004 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NJ9Ix-0005PF-Ay for qemu-devel@nongnu.org; Fri, 11 Dec 2009 12:29:23 -0500 Received: from mx20.gnu.org ([199.232.41.8]:42003) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NJ9Ix-0007h6-2w for qemu-devel@nongnu.org; Fri, 11 Dec 2009 12:29:23 -0500 Received: from mail.codesourcery.com ([38.113.113.100]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NJ9Iv-00089J-RQ for qemu-devel@nongnu.org; Fri, 11 Dec 2009 12:29:22 -0500 From: Nathan Froyd Date: Fri, 11 Dec 2009 09:29:20 -0800 Message-Id: <1260552560-30233-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH] target-mips: fix user-mode emulation startup List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Running programs with the MIPS user-mode emulator fails during dynamic loading, as floating-point instructions are not enabled in in env->hflags. Move the code for doing so from fpu_init to cpu_reset so the MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset setting env->hflags to MIPS_HFLAG_UM. The same end can be achieved by swapping the ordering of fpu_init and cpu_reset in cpu_mips_init, but it seemed better to consolidate the CONFIG_USER_ONLY code into a single location. Signed-off-by: Nathan Froyd --- target-mips/translate.c | 8 ++++++++ target-mips/translate_init.c | 8 -------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 9d62b64..f756ab9 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -8652,6 +8652,14 @@ void cpu_reset (CPUMIPSState *env) env->hflags = MIPS_HFLAG_UM; /* Enable access to the SYNCI_Step register. */ env->CP0_HWREna |= (1 << 1); + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + env->hflags |= MIPS_HFLAG_FPU; + } +#ifdef TARGET_MIPS64 + if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { + env->hflags |= MIPS_HFLAG_F64; + } +#endif #else if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot, diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index c950eab..3978908 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -524,14 +524,6 @@ static void fpu_init (CPUMIPSState *env, const mips_def_t *def) env->fpus[i].fcr0 = def->CP1_fcr0; memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); -#if defined(CONFIG_USER_ONLY) - if (env->CP0_Config1 & (1 << CP0C1_FP)) - env->hflags |= MIPS_HFLAG_FPU; -#ifdef TARGET_MIPS64 - if (env->active_fpu.fcr0 & (1 << FCR0_F64)) - env->hflags |= MIPS_HFLAG_F64; -#endif -#endif } static void mvp_init (CPUMIPSState *env, const mips_def_t *def) -- 1.6.3.2