From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NK8t4-0008O1-Gk for qemu-devel@nongnu.org; Mon, 14 Dec 2009 06:14:46 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NK8sy-0008Ls-LY for qemu-devel@nongnu.org; Mon, 14 Dec 2009 06:14:45 -0500 Received: from [199.232.76.173] (port=52024 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NK8sy-0008Lo-Gs for qemu-devel@nongnu.org; Mon, 14 Dec 2009 06:14:40 -0500 Received: from mail-ew0-f221.google.com ([209.85.219.221]:42433) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NK8sy-00020M-8P for qemu-devel@nongnu.org; Mon, 14 Dec 2009 06:14:40 -0500 Received: by ewy21 with SMTP id 21so1639361ewy.2 for ; Mon, 14 Dec 2009 03:14:38 -0800 (PST) From: nemesisofstate Date: Mon, 14 Dec 2009 12:09:13 +0100 Message-Id: <1260788953-30794-1-git-send-email-nemesisofstate@gmail.com> Subject: [Qemu-devel] [PATCH] correcting ARM CPSR register bit position comment List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: nemesis --- target-arm/cpu.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4a1c53f..910604f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -90,7 +90,7 @@ typedef struct CPUARMState { /* cpsr flag cache for faster execution */ uint32_t CF; /* 0 or 1 */ - uint32_t VF; /* V is the bit 31. All other bits are undefined */ + uint32_t VF; /* V is the bit 28. */ uint32_t NF; /* N is bit 31. All other bits are undefined. */ uint32_t ZF; /* Z set if zero. */ uint32_t QF; /* 0 or 1 */ -- 1.6.3.3