From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NKX3t-00076u-V5 for qemu-devel@nongnu.org; Tue, 15 Dec 2009 08:03:34 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NKX3o-0006zI-Ci for qemu-devel@nongnu.org; Tue, 15 Dec 2009 08:03:32 -0500 Received: from [199.232.76.173] (port=44812 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NKX3n-0006yw-QW for qemu-devel@nongnu.org; Tue, 15 Dec 2009 08:03:27 -0500 Received: from moutng.kundenserver.de ([212.227.126.186]:54563) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NKX3n-0000mg-6h for qemu-devel@nongnu.org; Tue, 15 Dec 2009 08:03:27 -0500 From: Stefan Weil Date: Tue, 15 Dec 2009 14:03:03 +0100 Message-Id: <1260882183-7398-1-git-send-email-weil@mail.berlios.de> Subject: [Qemu-devel] [PATCH] mips: No MIPS16 support for 4Kc, 4KEc cores List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nathan Froyd , Aurelien Jarno , QEMU Developers Fix regression introduced by d19954f46dfc262612c30e9534e660e953049487. 4Kc and 4KEc don't support MIPS16. Signed-off-by: Stefan Weil --- target-mips/translate_init.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 11bc47c..b710979 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -105,7 +105,7 @@ static const mips_def_t mips_defs[] = .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), + (0 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, .CP0_LLAddr_rw_bitmask = 0, @@ -147,7 +147,7 @@ static const mips_def_t mips_defs[] = .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), + (0 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, .CP0_LLAddr_rw_bitmask = 0, @@ -188,7 +188,7 @@ static const mips_def_t mips_defs[] = .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | - (1 << CP0C1_CA), + (0 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), .CP0_LLAddr_rw_bitmask = 0, -- 1.6.5