From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NSFVq-0003F9-B9 for qemu-devel@nongnu.org; Tue, 05 Jan 2010 14:56:18 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NSFVh-00034l-MF for qemu-devel@nongnu.org; Tue, 05 Jan 2010 14:56:12 -0500 Received: from [199.232.76.173] (port=43144 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NSFVd-00032J-3l for qemu-devel@nongnu.org; Tue, 05 Jan 2010 14:56:05 -0500 Received: from mx20.gnu.org ([199.232.41.8]:36480) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NSFVc-0005Iy-AM for qemu-devel@nongnu.org; Tue, 05 Jan 2010 14:56:04 -0500 Received: from gate.crashing.org ([63.228.1.57]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NRuuH-0007fp-59 for qemu-devel@nongnu.org; Mon, 04 Jan 2010 16:56:09 -0500 Subject: Re: [Qemu-devel] Re: [PATCH 1/6] Make config space accessor host bus trapable From: Benjamin Herrenschmidt In-Reply-To: <20100104213021.GC21488@redhat.com> References: <41679128-EE37-47DA-82F6-830A4C364183@suse.de> <20100103180609.GB8522@redhat.com> <472F306A-0699-401C-8E6A-8E79B86E4C95@suse.de> <1262551822.2173.267.camel@pasglop> <19BFDDD5-85E0-42EC-9D71-391CECC023F5@suse.de> <20100104104516.GD4672@valinux.co.jp> <20100104110758.GE8522@redhat.com> <1262635858.2173.371.camel@pasglop> <20100104211208.GA21488@redhat.com> <1262640330.2173.386.camel@pasglop> <20100104213021.GC21488@redhat.com> Content-Type: text/plain; charset="UTF-8" Date: Tue, 05 Jan 2010 08:53:52 +1100 Message-ID: <1262642032.2173.388.camel@pasglop> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Blue Swirl , Isaku Yamahata , Alexander Graf , Aurelien Jarno , QEMU Developers > Yes, but I think how you program your host to pci bridge is platform specific, > the standard (mostly) applies to what happens below the bridge. There's > no real standard for how PCI host bridge is connected to processor > AFAIK, it's by luck we can share code there at all. Well, yes and no ... there's a standard on how a PCI host bridge is connected in the sense that how normal MMIO accesses go through in term of endianness is well defined. How you actually issue config space cycles is a property of a given bridge. How you issue IO cycles as well in fact. Cheers, Ben.