From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NZnpr-0007te-Uq for qemu-devel@nongnu.org; Tue, 26 Jan 2010 11:00:12 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NZnpp-0007qq-89 for qemu-devel@nongnu.org; Tue, 26 Jan 2010 11:00:09 -0500 Received: from [199.232.76.173] (port=45567 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NZnpo-0007qO-PM for qemu-devel@nongnu.org; Tue, 26 Jan 2010 11:00:08 -0500 Received: from afflict.kos.to ([92.243.29.197]:36707) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NZnpo-0000VX-75 for qemu-devel@nongnu.org; Tue, 26 Jan 2010 11:00:08 -0500 From: Riku Voipio Date: Tue, 26 Jan 2010 16:00:03 +0000 Message-Id: <1264521604-2020-5-git-send-email-riku.voipio@iki.fi> In-Reply-To: <1264521604-2020-1-git-send-email-riku.voipio@iki.fi> References: <1264521604-2020-1-git-send-email-riku.voipio@iki.fi> Subject: [Qemu-devel] [PATCH 4/5] linux-user: Add access to TLS registers List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Riku Voipio From: Riku Voipio If you compile applications with gcc -mtp=cp15, __thread access's will generate an abort. Implement accessing allowed cp15.c13 registers on ARMv6K+ in linux-user. Signed-off-by: Riku Voipio --- target-arm/helper.c | 27 ++++++++++++++++++++++++++- 1 files changed, 26 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index b3aec99..68578ce 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -505,13 +505,38 @@ uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) { + int op2; + + op2 = (insn >> 5) & 7; + /* Allow write access to CP15 User RW Thread ID Register */ + if (arm_feature (env, ARM_FEATURE_V6K) && ((insn >> 16) & 0xf) == 13) { + switch (op2) { + case 2: + env->cp15.c13_tls1 = val; + return; + } + } cpu_abort(env, "cp15 insn %08x\n", insn); } uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) { + int op2; + /* Allow read access to CP15 User RW and RO Thread ID Registers */ + + op2 = (insn >> 5) & 7; + if (arm_feature (env, ARM_FEATURE_V6K) && ((insn >> 16) & 0xf) == 13) { + switch (op2) { + case 2: + return env->cp15.c13_tls1; + case 3: + return env->cp15.c13_tls2; + default: + goto bad_reg; + } + } +bad_reg: cpu_abort(env, "cp15 insn %08x\n", insn); - return 0; } /* These should probably raise undefined insn exceptions. */ -- 1.6.5