[Qemu-devel] [PATCH 0/4] linux-user-for-upstream patches

[Qemu-devel] [PATCH 0/4] linux-user-for-upstream patches

[Riku Voipio]

From: Riku Voipio <riku.voipio@nokia.com>

Some fixes to avoid hanging, make arm uname match selected
cpu, and fix cp15.c13 register for linux-user tls register
access.

Loïc Minier (1):
  linux-user: adapt uname machine to emulated CPU

Riku Voipio (3):
  fix locking error with current_tb
  linux-user: remove signal handler before calling abort()
  target-arm: refactor cp15.c13 register access

 Makefile.target        |    2 +-
 exec.c                 |   13 +++++++-
 linux-user/cpu-uname.c |   72 ++++++++++++++++++++++++++++++++++++++++++++++++
 linux-user/cpu-uname.h |    1 +
 linux-user/syscall.c   |    3 +-
 target-arm/helper.c    |   16 ----------
 target-arm/translate.c |   55 ++++++++++++++++++++++++++++++++++++
 7 files changed, 142 insertions(+), 20 deletions(-)
 create mode 100644 linux-user/cpu-uname.c
 create mode 100644 linux-user/cpu-uname.h

[Qemu-devel] [PATCH 1/4] linux-user: adapt uname machine to emulated CPU

[Riku Voipio]

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From: Loïc Minier <lool@dooz.org>

This patch for linux-user adapts the output of the emulated uname()
syscall to match the configured CPU.  Tested with x86, x86-64 and arm
emulation.

Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
Signed-off-by: Loïc Minier <lool@dooz.org>
---
 Makefile.target        |    2 +-
 linux-user/cpu-uname.c |   72 ++++++++++++++++++++++++++++++++++++++++++++++++
 linux-user/cpu-uname.h |    1 +
 linux-user/syscall.c   |    3 +-
 4 files changed, 76 insertions(+), 2 deletions(-)
 create mode 100644 linux-user/cpu-uname.c
 create mode 100644 linux-user/cpu-uname.h

diff --git a/Makefile.target b/Makefile.target
index 5c0ef1f..9dfc4c2 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -95,7 +95,7 @@ $(call set-vpath, $(SRC_PATH)/linux-user:$(SRC_PATH)/linux-user/$(TARGET_ABI_DIR
 
 QEMU_CFLAGS+=-I$(SRC_PATH)/linux-user -I$(SRC_PATH)/linux-user/$(TARGET_ABI_DIR)
 obj-y = main.o syscall.o strace.o mmap.o signal.o thunk.o \
-      elfload.o linuxload.o uaccess.o gdbstub.o
+      elfload.o linuxload.o uaccess.o gdbstub.o cpu-uname.o
 
 obj-$(TARGET_HAS_BFLT) += flatload.o
 obj-$(TARGET_HAS_ELFLOAD32) += elfload32.o
diff --git a/linux-user/cpu-uname.c b/linux-user/cpu-uname.c
new file mode 100644
index 0000000..23afede
--- /dev/null
+++ b/linux-user/cpu-uname.c
@@ -0,0 +1,72 @@
+/*
+ *  cpu to uname machine name map
+ *
+ *  Copyright (c) 2009 Loïc Minier
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+
+#include "qemu.h"
+//#include "qemu-common.h"
+#include "cpu-uname.h"
+
+/* return highest utsname machine name for emulated instruction set
+ *
+ * NB: the default emulated CPU ("any") might not match any existing CPU, e.g.
+ * on ARM it has all features turned on, so there is no perfect arch string to
+ * return here */
+const char *cpu_to_uname_machine(void *cpu_env)
+{
+#ifdef TARGET_ARM
+    /* utsname machine name on linux arm is CPU arch name + endianness, e.g.
+     * armv7l; to get a list of CPU arch names from the linux source, use:
+     *     grep arch_name: -A1 linux/arch/arm/mm/proc-*.S
+     * see arch/arm/kernel/setup.c: setup_processor()
+     *
+     * to test by CPU id, compare cpu_env->cp15.c0_cpuid to ARM_CPUID_*
+     * defines and to test by CPU feature, use arm_feature(cpu_env,
+     * ARM_FEATURE_*) */
+
+    /* in theory, endianness is configurable on some ARM CPUs, but this isn't
+     * used in user mode emulation */
+#ifdef TARGET_WORDS_BIGENDIAN
+#define utsname_suffix "b"
+#else
+#define utsname_suffix "l"
+#endif
+    if (arm_feature(cpu_env, ARM_FEATURE_V7))
+        return "armv7" utsname_suffix;
+    if (arm_feature(cpu_env, ARM_FEATURE_V6))
+        return "armv6" utsname_suffix;
+    /* earliest emulated CPU is ARMv5TE; qemu can emulate the 1026, but not its
+     * Jazelle support */
+    return "armv5te" utsname_suffix;
+#elif defined(TARGET_X86_64)
+    return "x86-64";
+#elif defined(TARGET_I386)
+    /* see arch/x86/kernel/cpu/bugs.c: check_bugs(), 386, 486, 586, 686 */
+    uint32_t cpuid_version = ((CPUX86State *)cpu_env)->cpuid_version;
+    int family = ((cpuid_version >> 8) & 0x0f) + ((cpuid_version >> 20) & 0xff);
+    if (family == 4)
+        return "i486";
+    if (family == 5)
+        return "i586";
+    return "i686";
+#else
+    /* default is #define-d in each arch/ subdir */
+    return UNAME_MACHINE;
+#endif
+}
diff --git a/linux-user/cpu-uname.h b/linux-user/cpu-uname.h
new file mode 100644
index 0000000..32492de
--- /dev/null
+++ b/linux-user/cpu-uname.h
@@ -0,0 +1 @@
+const char *cpu_to_uname_machine(void *cpu_env);
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index f2dd39e..9fb493f 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -82,6 +82,7 @@
 #include <linux/fb.h>
 #include <linux/vt.h>
 #include "linux_loop.h"
+#include "cpu-uname.h"
 
 #include "qemu.h"
 #include "qemu-common.h"
@@ -5739,7 +5740,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
             if (!is_error(ret)) {
                 /* Overrite the native machine name with whatever is being
                    emulated. */
-                strcpy (buf->machine, UNAME_MACHINE);
+                strcpy (buf->machine, cpu_to_uname_machine(cpu_env));
                 /* Allow the user to override the reported release.  */
                 if (qemu_uname_release && *qemu_uname_release)
                   strcpy (buf->release, qemu_uname_release);
-- 
1.6.5

[Qemu-devel] [PATCH 2/4] fix locking error with current_tb

[Riku Voipio]

From: Riku Voipio <riku.voipio@nokia.com>

Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
---
 exec.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/exec.c b/exec.c
index 76831a1..431e104 100644
--- a/exec.c
+++ b/exec.c
@@ -1537,15 +1537,15 @@ static void cpu_unlink_tb(CPUState *env)
     TranslationBlock *tb;
     static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
 
+    spin_lock(&interrupt_lock);
     tb = env->current_tb;
     /* if the cpu is currently executing code, we must unlink it and
        all the potentially executing TB */
     if (tb) {
-        spin_lock(&interrupt_lock);
         env->current_tb = NULL;
         tb_reset_jump_recursive(tb);
-        spin_unlock(&interrupt_lock);
     }
+    spin_unlock(&interrupt_lock);
 }
 
 /* mask must never be zero, except for A20 change call */
-- 
1.6.5

[Qemu-devel] [PATCH 3/4] linux-user: remove signal handler before calling abort()

[Riku Voipio]

From: Riku Voipio <riku.voipio@nokia.com>

Qemu may hang in host_signal_handler after qemu has done a
seppuku with cpu_abort(). But at this stage we are not really
interested in target process coredump anymore, so unregister
host_signal_handler to die grafefully.

Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
---
 exec.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/exec.c b/exec.c
index 431e104..eeb17d0 100644
--- a/exec.c
+++ b/exec.c
@@ -40,6 +40,7 @@
 #include "kvm.h"
 #if defined(CONFIG_USER_ONLY)
 #include <qemu.h>
+#include <signal.h>
 #endif
 
 //#define DEBUG_TB_INVALIDATE
@@ -1692,6 +1693,14 @@ void cpu_abort(CPUState *env, const char *fmt, ...)
     }
     va_end(ap2);
     va_end(ap);
+#if defined(CONFIG_USER_ONLY)
+    {
+        struct sigaction act;
+        sigfillset(&act.sa_mask);
+        act.sa_handler = SIG_DFL;
+        sigaction(SIGABRT, &act, NULL);
+    }
+#endif
     abort();
 }
 
-- 
1.6.5

[Qemu-devel] [PATCH 4/4] target-arm: refactor cp15.c13 register access

[Riku Voipio]

From: Riku Voipio <riku.voipio@nokia.com>

Access the cp15.c13 TLS registers directly with TCG ops instead of with
a slow helper. If the the cp15 read/write was not TLS register access,
fall back to the cp15 helper.

This makes accessing __thread variables in linux-user when apps are compiled
with -mtp=cp15 possible. legal cp15 register to acces from linux-user are
already checked in cp15_user_ok.

While at it, make the cp15.c13 Thread ID registers available only on
ARMv6K and newer.

Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
---
 target-arm/helper.c    |   16 --------------
 target-arm/translate.c |   55 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+), 16 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index b3aec99..27001e8 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -511,7 +511,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
 {
     cpu_abort(env, "cp15 insn %08x\n", insn);
-    return 0;
 }
 
 /* These should probably raise undefined insn exceptions.  */
@@ -1491,15 +1490,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
               tlb_flush(env, 0);
             env->cp15.c13_context = val;
             break;
-        case 2:
-            env->cp15.c13_tls1 = val;
-            break;
-        case 3:
-            env->cp15.c13_tls2 = val;
-            break;
-        case 4:
-            env->cp15.c13_tls3 = val;
-            break;
         default:
             goto bad_reg;
         }
@@ -1779,12 +1769,6 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
             return env->cp15.c13_fcse;
         case 1:
             return env->cp15.c13_context;
-        case 2:
-            return env->cp15.c13_tls1;
-        case 3:
-            return env->cp15.c13_tls2;
-        case 4:
-            return env->cp15.c13_tls3;
         default:
             goto bad_reg;
         }
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 5cf3e06..786c329 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2455,6 +2455,57 @@ static int cp15_user_ok(uint32_t insn)
     return 0;
 }
 
+static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
+{
+    TCGv tmp;
+    int cpn = (insn >> 16) & 0xf;
+    int cpm = insn & 0xf;
+    int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
+
+    if (!arm_feature(env, ARM_FEATURE_V6K))
+        return 0;
+
+    if (!(cpn == 13 && cpm == 0))
+        return 0;
+
+    if (insn & ARM_CP_RW_BIT) {
+        tmp = new_tmp();
+        switch (op) {
+        case 2:
+            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls1));
+            break;
+        case 3:
+            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls2));
+            break;
+        case 4:
+            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls3));
+            break;
+        default:
+            dead_tmp(tmp);
+            return 0;
+        }
+        store_reg(s, rd, tmp);
+
+    } else {
+        tmp = load_reg(s, rd);
+        switch (op) {
+        case 2:
+            tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls1));
+            break;
+        case 3:
+            tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls2));
+            break;
+        case 4:
+            tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls3));
+            break;
+        default:
+            return 0;
+        }
+        dead_tmp(tmp);
+    }
+    return 1;
+}
+
 /* Disassemble system coprocessor (cp15) instruction.  Return nonzero if
    instruction is not defined.  */
 static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
@@ -2489,6 +2540,10 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
         return 0;
     }
     rd = (insn >> 12) & 0xf;
+
+    if (cp15_tls_load_store(env, s, insn, rd))
+        return 0;
+
     tmp2 = tcg_const_i32(insn);
     if (insn & ARM_CP_RW_BIT) {
         tmp = new_tmp();
-- 
1.6.5

Re: [Qemu-devel] [PATCH 4/4] target-arm: refactor cp15.c13 register access

[Laurent Desnogues]

On Wed, Jan 27, 2010 at 1:49 PM, Riku Voipio <riku.voipio@iki.fi> wrote:
> From: Riku Voipio <riku.voipio@nokia.com>
>
> Access the cp15.c13 TLS registers directly with TCG ops instead of with
> a slow helper. If the the cp15 read/write was not TLS register access,
> fall back to the cp15 helper.
>
> This makes accessing __thread variables in linux-user when apps are compiled
> with -mtp=cp15 possible. legal cp15 register to acces from linux-user are
> already checked in cp15_user_ok.
>
> While at it, make the cp15.c13 Thread ID registers available only on
> ARMv6K and newer.
>
> Signed-off-by: Riku Voipio <riku.voipio@nokia.com>

Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>


Laurent

> ---
>  target-arm/helper.c    |   16 --------------
>  target-arm/translate.c |   55 ++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 55 insertions(+), 16 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index b3aec99..27001e8 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -511,7 +511,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
>  uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
>  {
>     cpu_abort(env, "cp15 insn %08x\n", insn);
> -    return 0;
>  }
>
>  /* These should probably raise undefined insn exceptions.  */
> @@ -1491,15 +1490,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
>               tlb_flush(env, 0);
>             env->cp15.c13_context = val;
>             break;
> -        case 2:
> -            env->cp15.c13_tls1 = val;
> -            break;
> -        case 3:
> -            env->cp15.c13_tls2 = val;
> -            break;
> -        case 4:
> -            env->cp15.c13_tls3 = val;
> -            break;
>         default:
>             goto bad_reg;
>         }
> @@ -1779,12 +1769,6 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
>             return env->cp15.c13_fcse;
>         case 1:
>             return env->cp15.c13_context;
> -        case 2:
> -            return env->cp15.c13_tls1;
> -        case 3:
> -            return env->cp15.c13_tls2;
> -        case 4:
> -            return env->cp15.c13_tls3;
>         default:
>             goto bad_reg;
>         }
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 5cf3e06..786c329 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -2455,6 +2455,57 @@ static int cp15_user_ok(uint32_t insn)
>     return 0;
>  }
>
> +static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
> +{
> +    TCGv tmp;
> +    int cpn = (insn >> 16) & 0xf;
> +    int cpm = insn & 0xf;
> +    int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
> +
> +    if (!arm_feature(env, ARM_FEATURE_V6K))
> +        return 0;
> +
> +    if (!(cpn == 13 && cpm == 0))
> +        return 0;
> +
> +    if (insn & ARM_CP_RW_BIT) {
> +        tmp = new_tmp();
> +        switch (op) {
> +        case 2:
> +            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls1));
> +            break;
> +        case 3:
> +            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls2));
> +            break;
> +        case 4:
> +            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls3));
> +            break;
> +        default:
> +            dead_tmp(tmp);
> +            return 0;
> +        }
> +        store_reg(s, rd, tmp);
> +
> +    } else {
> +        tmp = load_reg(s, rd);
> +        switch (op) {
> +        case 2:
> +            tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls1));
> +            break;
> +        case 3:
> +            tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls2));
> +            break;
> +        case 4:
> +            tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls3));
> +            break;
> +        default:
> +            return 0;
> +        }
> +        dead_tmp(tmp);
> +    }
> +    return 1;
> +}
> +
>  /* Disassemble system coprocessor (cp15) instruction.  Return nonzero if
>    instruction is not defined.  */
>  static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
> @@ -2489,6 +2540,10 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
>         return 0;
>     }
>     rd = (insn >> 12) & 0xf;
> +
> +    if (cp15_tls_load_store(env, s, insn, rd))
> +        return 0;
> +
>     tmp2 = tcg_const_i32(insn);
>     if (insn & ARM_CP_RW_BIT) {
>         tmp = new_tmp();
> --
> 1.6.5
>
>
>
>