[Qemu-devel] [PATCH 0/3] target-arm: Thumb(-2) exception support

[Qemu-devel] [PATCH 0/3] target-arm: Thumb(-2) exception support

[Rabin Vincent]

This series adds Thumb exception support and fixes a couple of instructions
related to it.

With these patches, QEMU can boot a Linux kernel built with Thumb-2.

Rabin Vincent (3):
  target-arm: fix thumb CPS
  target-arm: implement Thumb-2 exception return
  target-arm: support thumb exception handlers

 target-arm/helper.c    |    5 ++---
 target-arm/translate.c |   15 ++++++++++++---
 2 files changed, 14 insertions(+), 6 deletions(-)

[Qemu-devel] [PATCH 1/3] target-arm: fix thumb CPS

[Rabin Vincent]

The Thumb CPS currently does not work correctly: CPSID touches more bits
than the instruction wants to, and CPSIE does nothing.  Fix it by
passing the correct mask (the "affect" bits) and value.

Signed-off-by: Rabin Vincent <rabin@rab.in>
---
 target-arm/translate.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 786c329..10a516b 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -8898,7 +8898,7 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s)
                     shift = CPSR_A | CPSR_I | CPSR_F;
                 else
                     shift = 0;
-                gen_set_psr_im(s, shift, 0, ((insn & 7) << 6) & shift);
+                gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
             }
             break;
 
-- 
1.6.6

[Qemu-devel] [PATCH 2/3] target-arm: implement Thumb-2 exception return

[Rabin Vincent]

Support the "subs pc, lr" Thumb-2 exception return instruction.

Signed-off-by: Rabin Vincent <rabin@rab.in>
---
 target-arm/translate.c |   13 +++++++++++--
 1 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 10a516b..f0667e5 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -8001,8 +8001,17 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
                         gen_bx(s, tmp);
                         break;
                     case 5: /* Exception return.  */
-                        /* Unpredictable in user mode.  */
-                        goto illegal_op;
+                        if (IS_USER(s)) {
+                            goto illegal_op;
+                        }
+
+                        tmp = load_reg(s, rn);
+                        tmp2 = new_tmp();
+                        tcg_gen_movi_i32(tmp2, insn & 0xff);
+                        gen_helper_sub_cc(tmp, tmp, tmp2);
+                        gen_exception_return(s, tmp);
+                        dead_tmp(tmp2);
+                        break;
                     case 6: /* mrs cpsr.  */
                         tmp = new_tmp();
                         if (IS_M(env)) {
-- 
1.6.6

[Qemu-devel] [PATCH 3/3] target-arm: support thumb exception handlers

[Rabin Vincent]

When handling an exception, switch to the correct mode based on the
Thumb Exception (TE) bit in the SCTLR.

Signed-off-by: Rabin Vincent <rabin@rab.in>
---
 target-arm/helper.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 27001e8..434628b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -824,11 +824,10 @@ void do_interrupt(CPUARMState *env)
     env->spsr = cpsr_read(env);
     /* Clear IT bits.  */
     env->condexec_bits = 0;
-    /* Switch to the new mode, and switch to Arm mode.  */
-    /* ??? Thumb interrupt handlers not implemented.  */
+    /* Switch to the new mode, and to the correct instruction set.  */
     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
     env->uncached_cpsr |= mask;
-    env->thumb = 0;
+    env->thumb = !!(env->cp15.c1_sys & (1 << 30));
     env->regs[14] = env->regs[15] + offset;
     env->regs[15] = addr;
     env->interrupt_request |= CPU_INTERRUPT_EXITTB;
-- 
1.6.6