From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NgjG2-00089V-DT for qemu-devel@nongnu.org; Sun, 14 Feb 2010 13:31:50 -0500 Received: from [199.232.76.173] (port=43614 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NgjG1-000898-Ph for qemu-devel@nongnu.org; Sun, 14 Feb 2010 13:31:49 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NgjG1-000053-6q for qemu-devel@nongnu.org; Sun, 14 Feb 2010 13:31:49 -0500 Received: from mail-yw0-f194.google.com ([209.85.211.194]:32806) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NgjG0-00004x-UH for qemu-devel@nongnu.org; Sun, 14 Feb 2010 13:31:49 -0500 Received: by ywh32 with SMTP id 32so7208517ywh.14 for ; Sun, 14 Feb 2010 10:31:48 -0800 (PST) Sender: Rabin Vincent From: Rabin Vincent Date: Mon, 15 Feb 2010 00:02:36 +0530 Message-Id: <1266172357-9252-4-git-send-email-rabin@rab.in> In-Reply-To: <1266172357-9252-1-git-send-email-rabin@rab.in> References: <1266172357-9252-1-git-send-email-rabin@rab.in> Subject: [Qemu-devel] [PATCH 3/3] target-arm: support thumb exception handlers List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rabin Vincent When handling an exception, switch to the correct mode based on the Thumb Exception (TE) bit in the SCTLR. Signed-off-by: Rabin Vincent --- target-arm/helper.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 27001e8..434628b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -824,11 +824,10 @@ void do_interrupt(CPUARMState *env) env->spsr = cpsr_read(env); /* Clear IT bits. */ env->condexec_bits = 0; - /* Switch to the new mode, and switch to Arm mode. */ - /* ??? Thumb interrupt handlers not implemented. */ + /* Switch to the new mode, and to the correct instruction set. */ env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; env->uncached_cpsr |= mask; - env->thumb = 0; + env->thumb = !!(env->cp15.c1_sys & (1 << 30)); env->regs[14] = env->regs[15] + offset; env->regs[15] = addr; env->interrupt_request |= CPU_INTERRUPT_EXITTB; -- 1.6.6